Memory Device Control for self-Refresh Mode

To ensure that a memory device operates in self-Refresh mode, the memory controller implements des (1) A normal-mode output buffer for driving a clock enable signal cke onto the memory device's cke input and (2) a power island for driving a clock enable signal cke_prime onto that same input. to power down the memory controller, the normal-mode output buffer drives signal cke low, then the power island drives signal cke_prime low, then the memory controller (memory t for the power Island) is powered down. the power island continues to drive the memory device's cke input low to ensure that the memory device stays in self-Refresh mode while the memory controller is powered substantially off. to resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal cke low, then the power Island is disabled, then the memory controller resumes normal operations of the memory device.

Background of the exception1. field of the exception

The present identifier tion relates to electronics, and, in particle, to memory devices having self-Refresh modes.

2. Description of the related art

In typical computer hardware ubuntures, an integrated circuit (IC) memory device chip is controlled by a separate IC memory controller chip that controls the writing of data to and the reading of data from the memory device during normal operations of the memory device. some memory devices are capable of operating in a self-Refresh mode in which the memory device maintains its stored data without any active command from the memory controller, such as when the memory controller is powered off.

For some memory devices, such as ddr1 and DDR2 registered dual in-line memory modules (rdimms) defined by joint Electron Device Engineering couneller (JEDEC) standards jesd79f and JESD79-2E, respectively, where DDR stands for "double data rate, "the memory device's reset signal can be used to keep the memory device in self-Refresh mode by holding the memory device's clock enable (cke) line low while allowing the memory controller to be powered down. for other memory devices, such as ddr3 rdimm memory devices defined by JEDEC Standard JESD79-3C, asserting the reset signal takes the memory device out of self-Refresh mode. as such, when the memory controller is powered off, the reset signal cannot be used to keep the memory device in self-Refresh mode, thereby jeopardizing the integrity of the data stored in the memory device.

Summary of the partition tion

In one embodiment, the present injection is apparatus comprising a memory controller for controlling a memory device having a clock enable (cke) input. the memory controller comprises first circuitry and second circuitry. the first circuitry is adapted to apply a first cke signal to the cke input during a normal operating mode. the second circuitry is adapted to apply a second cke signal to the cke input during a self-Refresh operating mode. during the self-Refresh operating mode, (I) the first circuitry is powered off and (ii) the second circuitry is powered on to drive the second cke signal to a self-Refresh signal level for the memory device.

In another embodiment, the present injection is a method for controlling a memory device having a clock enable (cke) input. the method comprises (a) using first circuitry to apply a first cke signal to the cke input during a normal operating mode and (B) using second circuitry to apply a second cke signal to the cke input during a self-Refresh operating mode. during the self-Refresh operating mode, (I) the first circuitry is powered off and (ii) the second circuitry is powered on to drive the second cke signal to a self-Refresh signal level for the memory device.

Detailed description

As used in this specification, the term "powered off" refers to a State of an integrated circuit (IC) chip in which no power is applied to the chip. the term "powered on" refers to a State in which power is applied to the chip. the term "Powering Up" refers to a transition from the powered-off state to the powered-on state, while the term "Powering Down" refers to a transition from the powered-on state to the powered-off state.

Fig. 1? Shows a Simplified Block dimo-of memory circuitry?100, According to one embodiment of the present tion. Memory circuitry?100? Between des ddr3 rdimm memory device?102, Memory controller?104, Power module?106, And reset controller?108. Memory controller?104? Controls the writing of data to and the reading of data from memory device?102. Power module?106? Provides power to memory device?102? Via power lines?112? And to memory controller?104? Via main power lines?114? And backup power lines?116. Reset controller?108? Controls the operations of memory controller?104? Via control lines?118-124.

In addition to other circuitry not shown in? Fig. 1, memory controller?104? Between des output buffers?126, Application logic?128, And cke power Island?130. Application logic?128? Controls the operations of output buffers?126, Which drive signals into memory device?102, Including clock enable signal cke via signal line?132? At the memory devices cke input. cke power Island?130? Includes isolation logic?134And output buffers?136. Isolation logic?134? Controls the operations of output buffers?136, Whose outputs are connected to the same signal lines as the outputs of output buffers?126, Including clock enable signal cke_prime, which is connected to the same signal line?132? That sums es the cke signal from a corresponding one of output buffers?126. Note that, in general, connections cocould be made on the die or in the package routing. In general, the corresponding buffer?126? Can be used to drive the cke signal onto signal line?132, When en the corresponding buffer?136? Is disabled, and vice versa. in addition, both corresponding buffers can be used simultaneously to drive equivalent output signals (I. E ., the cke and cke_prime signals both high or both low) onto signal line?132.

Although? Fig. 1? Shows memory circuitry?100? Having separate components, in general, two or more of those components may be implemented in a single integrated system-on-a-chip (SOC ).

Memory circuitry?100? Supports two different modes of operation: normal operating mode and self-Refresh operating mode.

1. During the normal operating mode:

• Memory device?102? And memory controller?104? Are both fully powered on;
• Application logic?128? Controls the operations of output buffers?126To drive appropriate signals into memory device?102. For example and in particle, in order for memory controller?104? To be able to write data to and read data from memory device?102? During the normal operating mode, application logic?128? Controls output buffers?126? To toggle the cke signal on signal line?132; And
• Reset controller?108? And isolation logic?134? Ensure that output buffers?136? Are disabled .?

1. During the self-Refresh operating mode:

• Memory device?102? Is fully powered on;
• Most but not all of memory controller?104? Is powered off. For example and in particle, output buffers?126? And application logic128? Are powered off, while cke power Island?130? Remains powered on; and
• Reset controller?108? And isolation logic?134? Control the operations of output buffers?136? To drive appropriate signals into memory device?102. For example and in particle, in order for memory device?102? To remain in its self-Refresh mode, output buffers?136Are controlled to drive the cke_prime signal low on signal line?132.

Fig. 1? Indicates, via circled reference numbers, the sequence of operations to transition memory circuitry?100? From its normal operating mode into its self-Refresh operating mode, and vice versa. In particle, memory circuitry?100? Can be transitioned from its normal operating mode into its self-Refresh operating mode (I. e., a power-down transition) by the following sequence of events:

• (1) transition is initiated by a system-level event, resulting in reset controller?108? Asserting low-power-mode signal lowpower_mode on control line?118.
• (2) In response to the assertion of the lowpower_mode signal, application logic?128? Controls output drivers?126? To place memory device?102? Into its self-Refresh mode, including driving the cke signal low on signal line?132.
• (3) Application logic?128? Activates cke power Island?130.
• (4) reset controller?108? Enables output drivers?136? Via control line124, Which results in isolation logic?134? Controlling output drivers136? To drive the cke_prime signal low on signal line?132. Note that, at this time, both corresponding output drivers?126? And?136Simultaneously drive signal line?132? Low.
• (5) reset controller?108? Asserts system-reset signal sys_reset via control line?120. Asserting the sys_reset signal causes application logic?128? To place output buffers?126? Into their initial state to ensure that output buffers?126? Drive the cke signal low.
• (6) reset controller?108? Asserts clock-Disable signal clock_disable via control line?122? To disable the clocks (not shown) in memory controller?104.
• (7) reset controller?108? Opens switch?138? To switch off power from power module?106? To memory controller?104? Via main power lines114, Which powers down most of memory controller?104, Including output buffers?126? And application logic?128.

Note that power module?106? Continues to provide power to memory device?102? Via power lines?112? And to cke power Island?130? Via backup power lines?116, Such that isolation logic?134? Controls output buffers?136To drive the cke_prime signal low to enable memory device?102? To remain in its self-Refresh mode .? Note that the seven steps involved in the power-down transition may be implemented in a different order. for example, the order of steps (2) and (3) can be reversed. note further that some of the steps may be optional. for example, step (5) is provided as a safety measure, but may be omitted in light of STEP (2 ).

In addition, referring to the same circled reference numbers in? Fig. 1, but in descending order (with the exception of steps (1) and (2), memory circuitry?100Can be transitioned from its self-Refresh operating mode back into its normal operating mode (I. e., a power-up transition) by the following sequence of events:

• (7) reset controller?108? Closes switch?138? To switch back on power from power module?106? To memory controller?104? Via main power lines?114, Which fully powers up memory controller?104, Including output buffers?126? And application logic?128. Note that power module?106? Continues to provide power to memory device102? Via power lines?112? And to cke power Island?130? Via backup power lines?116, Such that isolation logic?134? Controls output buffers?136? To continue to drive the cke_prime signal low to enable memory device?102? To remain in its self-Refresh mode.
• (6) reset controller?108? De-asserts clock-Disable signal clock_disable via control line?122? To re-enable the clocks (not shown) in memory controller?104.
• (5) reset controller?108? De-asserts system-reset signal sys_reset via control line?120. De-asserting the sys_reset signal causes application logic?128? To re-Initialize output buffers126? For resumption of normal operations. Note that, at initialization, output buffers?126? Drive the cke signal low. At this time, both corresponding output drivers?126? And?136? Simultaneously drive signal line?132? Low.
• (4) reset controller?108? Disables output drivers?136? Via control line124.
• (3) Application logic?128? Deactivates cke power Island?130.
• (1) reset controller?108? De-asserts the lowpower_mode signal via control line?118.
• (2) In response to the de-assertion of the lowpower_mode signal, application logic?128? Controls output drivers?126? To release memory device?102? From its self-Refresh mode for resumption of normal operations, including driving the cke signal as needed .?

Note that, here, too, the seven steps involved in the power-up transition may be implemented in a different order. for example, the order of STEP (3) can be implemented after steps (1) and (2 ).

Memory circuitry?100? Enables memory controller?104? To be substantially powered down while maintaining the integrity of the data stored in memory device?102.

In one implementation, each of elements?102-108? Of? Fig. 1? Is a discrete electronic module mounted on a circuit board and interconnected via suitable board traces. memory controller?104? May be part of a larger integrated circuit module that provides, in addition to the control of memory device?102, Other functions related to other system elements not shown in? Fig. 1. Similarly, power module?106? May provide power to other system elements not shown in? Fig. 1, including other memory devices.

Although the present tion has been described in the context of memory circuitry?100? Of? Fig. 1? Having a single ddr3 rdimm memory device, it will be understood that, in general, the present partition can be implemented for any suitable type of memory topology having one or more memory devices, where those memory devices can be rdimms, such as ddr1, DDR2, or ddr3 rdimms, or other suitable on-board devices.

Src = https://www.google.com.hk/patents/US8139433