Memory Hierarchies (1)

As we know, a simple computer system model is the CPU execution instruction, while the memory stores the instructions and data for the CPU.
In a simple model, the memory system is a linear byte array, and the CPU is able to access each memory location within the constant time range. Such a simple model does not effectively reflect the way in which modern systems actually work.

In fact, a memory system is a hierarchical structure of storage devices with different capacity, cost, and access times. The CPU registers hold the most commonly used data. Small fast cache memory near the CPU as part of the buffer of data and instructions stored in a relatively slow main memory (referred to as memory). Main memory temporarily stores data stored on a slow disk with a larger capacity. These disks are often used as buffer areas for data stored on disks or tapes of other machines connected over the network.

It is important to note that cache memory is the buffer zone between the CPU and main memory, which has the greatest impact on the performance of the application. Storage Technology: 1. Random access Memory (RAM): Random access memory is divided into two categories, static (SRAM) and dynamic (DRAM). Static is faster than dynamic, but also more expensive.

SRAM is used as a cache memory, either on the CPU or under the CPU. DRAM is used as a frame buffer for primary storage and also as a graphics system. Typically, a desktop system has no more than a few megabytes of SRAM, but the DRAM is hundreds of trillion or thousands of trillion. to better illustrate the characteristics and differences of DRAM and SRAM, here's a comparison:

A. SRAM stores each bit in a bistable memory unit. Each unit is implemented using a six-transistor circuit. This circuit has such a property that it can be kept indefinitely in one of two different voltage configurations or states. Its stability is good, that is, as long as there is electricity, it will always maintain its value. Even if there is interference (such as electronic noise) to disturb the voltage, the circuit reverts to a stable value when the interference is eliminated.

B. DRAM stores each bit as a charge to a capacitor, which is very small. DRAM memory can be made very dense: Each unit consists of a capacitor and an access transistor. However, unlike SRAM, the DRAM memory unit is very sensitive to interference, and when the voltage of the capacitor is disturbed, it will never recover. Exposure to light can cause a change in the capacitance voltage. There are many causes of leakage, which causes the DRAM to lose its charge again, so it is discontinuous. The memory system must be periodically read out and then rewritten to flush every bit of memory.
C.sram does not need to be refreshed, its access is faster than DRAM, and is insensitive to interference such as light and electrical noise. The cost is that SRAM uses more transistors than DRAM, so it's less dense and more expensive to consume.

Well, based on the simple introduction above, let's talk about the traditional dram:

The cells in the DRAM chip are: bits.
All the bits in the DRAM are divided into D-cells.
Each of the units is made up of w bits.
In other words, a DXW dram stores the DW bit information in total.

Each of the cells is tangible such as (I,J) address, where I is the row, J represents the column.
The information flows into and out of the chip through the external connector of the PIN, and each pin carries a bit of signal. A 2-bit row and column cell address is carried by 2 addr pins.

The following is a high-level view of the 128-bit 16x8 DRAM chip, with a shaded box representing the hyper-Unit at ():

Among them, there are d=16 units, each of which has a w=8 bit.

Each DRAM chip is connected to a circuit called a storage controller that can transmit a w bit (the contents of a single unit) to each DRAM chip or a w bit from each dram at a time.
To describe this transfer and outgoing process, I made a simple process illustration, as follows:

The storage controller sends the line address dram, and then the column address. DRAM sends the contents of the hyper-Unit to the controller as a response.

Also, note that RAS and CAS requests share the same DRAM address pins. One reason for circuit designers to organize DRAM into two-dimensional arrays instead of linear arrays is to reduce the number of pins on the chip, which has the disadvantage of having to send addresses in two steps, which increases the access time.