Memory Management: Physical Address Extension (PAE) paging mechanism

Abstract: Intel increases the processor's addressing capability to 2^36=64GB by increasing the number of pins from 32 to 36 on the processor, while the number of linear addresses is still 32 bits, which requires a new paging mechanism. Starting with the Pentium Pro processor, Intel introduced a PAE mechanism, and another called the page size extension mechanism (PSE) was introduced in Pentium III, but Linux was not adopted, and this article does not discuss it.

This article source: Memory Management: Physical Address Extension (PAE) paging mechanism http://blog.csdn.net/trochiluses/article/details/12853027

64GB of RAM is divided into 2^24 page boxes, the Physical Address fields of page table entries are extended from 20 bits to 24 bits, each page table entry must contain 12 flag bits (fixed) and 24 physical

Address bit (36-12), a total of 36 bits, so each page table entry must be extended from 32 bits to 64 bits (36-bit >32 bits, taking into account alignment, so the page table entries should be enlarged by one to 64 bits).

in the case of 4KB regular paging, because each page table item size is 64, the original 4K size of the page table can only contain 512 table items, which takes up

9 bits in a bit-linear address, in the same way, because the page catalog item has the same structure as the page table entry, the higher-level page catalog table can contain only 512 page table items, which also occupies

9 bits in a 32-bit linear address, at which point the remaining digits of the linear address are: 32 bits (total number of digits)-12 bits (in-page offset)-9 bits (indicates the index in the page table)-9 bits

(indicates the index in the page catalog table) = 2 bits, and Linux introduces a new level of page table (PDPT) for the pages of the directory pointer table, consisting of 4 64-bit table entries, the remaining

the 2-bit is used to point to one of the 4 items in the PDPT.

The following 4 graphs detail the structure of the page table in 4 cases (from Wikipedia)

page table structure for 4K paging under PAE is not enabled

Page Table structure for 4M paging under PAE is not enabled

Enable page table structure for 4K paging under PAE

Enable page table structure for 2M paging under PAE

the mapping process for linear addresses is as follows:

1) CR3: Point to a PDPT base address

2) Address 31~30: Determine PDPT

3) Address 29~21: Determine one of the page catalog entries

here, a branch occurs:

A. If the PS flag bit of the page catalog entry equals 0, the page size is 4K

4) Address 20~12: Determine an item in the page table

5) Address 11~0: Determine the offset

B. If Ps=1, enable large pages

4) address 20~0: Determines the offset in the 2M page.