* ******* 8086 *******
16-bit host, 20 address lines, addressing 1 MB memory (20 times), 2 16 I/O Ports
CPU Internal Structure
8086: Biu (Bus Interface Unit) Bus Interface Unit
Eu (Execution Unit) Execution Unit
8088: External 8-bit command buffer with only 4 bytes
Working principle:
1. Biu obtains the address from the internal register. For example, CS: the IP address is CS * 16 + and the IP address is sent to the 6-byte instruction buffer.
2. The EU extracts the address from the instruction buffer and performs corresponding I/O cycle operations.
3. When the 6-byte command is full, Biu is idle.
4. If the jump/call operation exists during execution, the queue is voided. In other cases, the EU/Biu performs the operation in parallel.
5. The arithmetic logic component (ALU) completes the transfer of computing results to the general memory Reader/Temporary memory/external I0 interface.
Register:
SP pointer register:
1. Specify the stack top unit through the SS: SP Logical Address
2. Change the pointer through the operation data
> Push-offset
> Pop + offset
BP pointer register: SS: BP specifies a pointer through a logical address
Si, di (Source/target address register ):
DS: Si refers to the first address of the source string
ES: Di points to the target string
IP Address: The address pointing to the next command
CS: the IP address cannot be determined by the system.
SS: BP indicates that the segment register can be specified.
Flag> Status flag control flag
Cf carry flag: generates a carry-out position. cf is set to 1.
ZF zero flag: The result is 0. ZF sets 1.
SF sign: If two numbers are negative, set it to 1
PF parity sign (even sign): if the number of digits for 1 is even, set 1
Of Overflow flag: If the signed computing result overflows, set it to 1.
AF secondary carry sign/TF trap sign/if sign (Interrupt sign)/DF direction sign
Pin Function: 40 pins
Minimum Operating Mode-single processor
Maximum operating mode-multi-processor
Nm/MX = 0 Max mode = 1 min Mode
Time-sharing 16 data lines and address lines
8086:
> AD15-AD0 a Data Bus (bidirectional) d address bus (unidirectional pointing from CPU to others)
T1: transmit address t2: idle t3t4: transmit data
> Ad19/S6-AD16/S3 address/status line AD0-AD15> Io
S6 is always 0 S5 indicates that the s4s3 segment register is interrupted
> RD reading signal WR writing signal M/io read memory/IO the former is 1 and the latter is 0
> INTA interrupt response signal
> DT/r Data Transmission Signal
> Bhe/S7 Bus high performance/status
Bhe selects high byte AD15-AD8 for 0
A0 is 0 select low byte AD7-AD0 (if both are 0, are useful if not 0 is invalid)
8086 access: only obtain the even address body. If it is an odd address body, it must be obtained twice.
8088: AD7-AD0
Microcomputer principle (2) 8086
