Mini2440 bare metal trial-IIC controls EEPROM data transmission, mini2440iic

Mini2440 bare metal trial-IIC controls EEPROM data transmission, mini2440iic
Content:

Write 0x00-0xff to the internal address of EEPROM (AT24C02), and then read the data.

Iic bus introduction:

The IIC (Inter-IntegratedCircuit, I2C) bus is a two-line serial bus developed by PHILIPS to connect the microprocessor and its peripheral devices. On the iic BUS, only two lines are required: the serial data line SDA and the serial clock line SCL to complete communication.

IIC highlights

1. Clear the IIC interrupt mark statement rIICCON & = ~ 0x10; be sure to read the back of the write register IICDS. The interrupt occurs after the read/write register;

2. Because the read speed of the EEPROM is not fast, a short delay function is required for each read/write interruption;

3. When reading data from AT24C02A,After a slave device address with a READ command is sent, AT24C02A returns a response from the device address or the device memory address. Therefore, you must read this byte and discard it, because it is not the information we want to read;

4. According to the time sequence of AT24C02A, when sending the slave device address byte, its bytes indicate 0 to write, and 1 to read. But for the s3c2440, it doesn't matter if you do not need to set this bit manually, that is, if the value of 0 is 1, it doesn't matter because this bit is determined by the s3c2440 Based on the sending mode of the master device or the receiving mode of the master device.Automatic settings. (0xa0 is used by default );

EEPROM Introduction

The AT24CXX series is an EEPROM with an iic bus interface, including AT24C01/24/60/16. Its capacity (bits x page) is 02/08x128x8/256x8/1024x8 /; for AT24C02A, all the three-address lines are written to death, because eight-address lines are sufficient for read/write operations. Therefore, the three-address lines are written to death as slices, for AT24C02A, the first three address lines must be written to the dead, and the last two addresses can be used as internal page addresses. Because the size of AT24C02A exceeds 256 bytes, 8 is addressing and cannot be used in all the space in the chip. Therefore, the program determines the next two digits.

Write Data in the EEPROM

When writing data, AMR9 acts as the main device, and the EEPROM is from the device

The first write byte method (this method is used in my program ):

Writing a byte actually requires sending three data records. In this process, the master device is in the sending status. The first data is the device address. Second data-the deviation between the first address of the EEPROM to be written by ARM9.

Transfer address. Third data-specific data to be written into the EEPROM. The last stop.

Method 2:

In fact, writing pages should be consistent with writing byte. the first data is the device address. Second data-the offset of the first address (but this address is the first address) relative to the first address of the data storage in the EEPROM to be written by ARM9.

The AT24C02 page is 8 bytes, And the AT24C04/08 page is 16 bytes. Therefore, when writing a page, you can write a maximum of one page. If you write too many pages, it will start from the first address again, and the previously written pages will be overwritten .). Third, Fourth, data -- the data you want to write into the EEPROM. Last stopped

Read data in EEPROM

The iic is automatically set when the master device is still ARM9. the slave device is EEPROM, which is in the sending or receiving status;

First, read the current address data:

The first data -- (the master device is in the active status now) is sent from the device address,

The second data -- (the master device is in the receiving status). When receiving data, note that there is no ack. Then stop. (Data is stable when no ack is generated. Why reading IIC?

I need to read the experiment twice at last. I just need to perform the experiment for the last time ,)

The second method of random data reading: (this method is used in my program)

The first data -- (the master device is in the active state) sends a slave device address. The first device address is used to match a device. It is also called a "dummy" byte write sequence in this document.

The second data-(the master device is in the active state) sends an offset address to the first address of the data to be read in the EEPROM relative to the data storage.

The third data -- (the master device is in the active state) sends a slave device address. This is a specific requirement for sending .. (The master device is configured as the receiving device .)

Status of the entire master device.

Fourth data-the data to be read (the master device is in the receiving status. It is also a no ack, similar to reading the current address. And then stop.

The third read sequence address (page read ):

The first data -- (the master device is in the sending status), sends the device address, and configures the master device to be in the receiving status. Prepare for receiving data later

Second, Third · Data -- (the master device is in the receiving status), each of the preceding data will send an ACK, And the last data is a no ack. Then stop.

In the above cases, we should pay attention to the adjustment of the status of the master device and the handling of no ack. We will see the case programs in the future to clearly see how to handle them.

Code block

# Include "def. h "# include" 2440addr. h "# include" 2440lib. h "static unsigned int I, j, save_E, save_PE; static U8 data [256]; static volatile int flag; // used to identify whether a response signal is received, 0 /***************************** ********************************** IIC initialization function **** **************************************** * *****************/void iic_init (void) {rGPECON | = 0xa0000000; // GPE15: IICSDA, GPE14: IICSCL (rGPEUP [] No Upper-pull option) // [7] = 1 allows a response to occur [6] = 0 IICCLK = fPCLK/16 PCLK 50 MHz, IICCLK = 3.17 MHz, tx Clock = 0.198 MHz // enable iic bus Tx/Rx interrupt enable IICCON [] = 16 rIICCON = (1 <7) | (0 <6) | (1 <5) | (0xf); rIICADD = 0x10; // The slave address represents the address when 2440 is used as the slave device, in this case, 2440 exists as a master device, so it does not work. RIICSTAT = 0x10; // IIC bus data output enabling read/write rIICLC = (1 <2) | (1 ); // enable the five clock latencies of the filter }/***************************** ********************************** IIC interrupt function **** **************************************** * ****************/void _ irq Iic_isr (void) {flag = 0; rSRCPND = 0x1 <27; // clear interrupt rINTPND = 0x1 <27;} void iic_isr (void) {rINTMSK & = ~ (0x1 <27); pISR_IIC = (unsigned) Iic_isr; // interrupt entry }/********************************** * *************************** write data in the EEPROM ******** **************************************** * ************/void Wr24C080 (U32 slvAddr, u32 addr, U8 data) {flag = 1; // The following are response flag signs. Location 1 rIICDS = slvAddr; // ** device address (the address of the EEPROM is 1010) rIICSTAT = 0xf0; // sending mode of the master device, write) generates the starting signal rIICCON & = ~ 0x10; // The following are the clear interrupt mark while (flag = 1) // when the sending is completed from the address, the ACK signal is received, set this flag to 0 Delay (1); flag = 1; rIICDS = addr; // offset address rIICCON & = ~ 0x10; while (flag = 1) // when the sending from address is complete, the ACK signal is received, and the flag is set to 0 Delay (1) in the interrupt processing function ); flag = 1; rIICDS = data; // The specific data to be written to rIICCON ~ 0x10; while (flag = 1) // when the sending from address is complete, the ACK signal is received, and the flag is set to 0 Delay (1) in the interrupt processing function ); rIICSTAT = 0xd0; // Stop MasTx condition rIICCON = 0xaf; // Resumes IIC operation. delay (1 );} /*************************************** ************* **************************************** * *******/void Rd24C080 (U32 slvAddr, u32 addr, U8 * data) {unsigned char temp; flag = 1; rIICDS = slvAddr; // Device Address (the address of the EEPROM is 1010) rIICSTAT = 0xf0; // The sending mode of the master device is used to send slvAddr and addr, and start rIICCON & = ~ 0x10; while (flag = 1) // when the sending from address is complete, the ACK signal is received, and the flag is set to 0 Delay (1) in the interrupt processing function ); flag = 1; rIICDS = addr; // offset address rIICCON & = ~ 0x10; while (flag = 1) // when the sending from address is complete, the ACK signal is received, and the flag is set to 0 Delay (1) in the interrupt processing function ); flag = 1; rIICDS = slvAddr; // the address of the slave device. This is a specific requirement for sending .. (The master device is configured as the receiving device here), // This sending device address is used to adjust the status of the master device at the same time. RIICSTAT = 0xb0; // The receiving mode of the master device is used to receive data and start rIICCON & = ~ 0x10; while (flag = 1) // when the sending from address is complete, the ACK signal is received, and the flag is set to 0 Delay (1) in the interrupt processing function ); // Note: reading the following byte must be performed, because after sending the address of the slave device with the READ command, // AT24C02A returns a response from the device address or the device memory address. Therefore, read the byte and discard it because it is not the information we want to read; flag = 1; // flag position 1 temp = rIICDS; // discard the first rIICCON & = ~ 0x10; // The while (flag) Delay (1); rIICCON = 0x2f; // Resumes IIC operation with NOACK. * data = rIICDS; Delay (1); rIICSTAT = 0x90; // Stop MasTx condition rIICCON = 0xaf; // Resumes IIC operation. delay (1 );} /*************************************** * ********************* IIC submain function ************* **************************************** * *******/void IIC (void) {Uart_Printf ("\ n *** iic test *** \ n"); // Delay (1000); // 1 // protect the field save_E = rGPECON; save_PE = rGPEUP; iic_init (); // IIC initializes iic_isr (); // IIC interrupts Uart_Printf ("writing data to EEPROM \ n "); // write data to EEPROM I for (I = 0; I <256; I ++) {Wr24C080 (0xa0, (U8) I, I); Delay (1 );} // note that the latency is not low. Otherwise, some data cannot be written. for (I = 0; I <256; I ++) data [0] = 0; // initialize data [I] Uart_Printf ("read EEPROM data \ n"); // The EEPROM reads data to data [I] for (I = 0; I <256; I ++) {Rd24C080 (0xa0, (U8) I, & (data [I]); Delay (1) ;}for (I = 0; I <16; I ++) // print the data [I] Array {Uart_Printf ("\ n"); for (j = 0; j <16; j ++) uart_Printf ("% 2x", data [I * 16 + j]);} // restores the rINTMSK | = 0x1 <27; rGPEUP = save_PE; rGPECON = save_E; while (1 ){}}

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The data storage and reading of single chip microcomputer EEPROM, the specific ideas for reading the latest 10 sets of data

1. I don't know how you display it, whether it is displayed on the LCD or printed in the serial port,
2. I don't know if you want to save the ten pieces of data that have been measured many times or not,

The read/write data of eepROM is implemented by IIC. Generally, the IIC address is fixed, and the second address is the address of the location to be read,

The detailed steps are as follows:
Read operation:
1: The IIC write address for sending data. As for the IIC protocol, it is not described much,
2: Send the address to read,
3: Send the IIC read address, that is, add 1 to the write address
4: Read data. It depends on the hardware-implemented protocol or the I/O-simulated protocol during your protocol. If the hardware-implemented protocol is used, simply read the register buff, if it is simulated by software, the latency should be well calculated so that the sampling can be accurate.

The four steps require the IIC protocol to start, transmit data, wait for the response, and end.

Lehua n21b77tv iic bus eeprom data

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