MIPI Commissioning Experience

Reprinted from http://blog.csdn.net/g_salamander/article/details/9163455

Here are some of the lessons learned from debugging MIPI Dsi/csi In recent months, as the protocols have specialized documentation, so here are some common points of knowledge:

First, d-phy

1. Transmission mode

LP (low-power) mode: For transmitting control signals up to a maximum rate of ten MHz

HS (high-speed) mode: for high-speed data transmission, rate range [at 1Gbps] per Lane

The minimum transmission unit is 1 bytes, with a small end and LSB FIRST,MSB last.

2. Lane states

* LP mode has 4 statuses: LP00, LP01 (0), LP10 (1), LP11 (Dp, Dn)

* HS Mode has 2 states: HS-0, HS-1

The data sent by the HS transmitter LP receivers see the LP00,

3. Lane levels

* lp:0 ~ 1.2V

* hs:100 ~ 300mv,hs Common level = 200mv,swing = MV

4. Operation mode

There are 3 possible modes of operation on the data line: Escape mode, high-speed (Burst) mode and Control mode, and the following is the timing required to enter the appropriate mode from the stop state:

* Escape Mode Enter timing: lp11→lp10→lp00→lp01→lp00, exit timing: LP10→LP11

When entering Escape mode a 8-bit entry command is required to indicate the requested action, such as the need to send cmd:0x87 for low-speed data transmission, and to send cmd:0x78 into ultra-low-power mode. LP Communication in DSI uses only Data Lane 0.

* High-speed mode enters timing: Lp11→lp01→lp00→sot (0001_1101), exit timing: EOT→LP11, timing diagram is as follows:

* Turnaround Entry timing: lp11→lp10→lp00→lp10→lp00, exit timing: LP00→LP10→LP11

This is the time sequence to turn on BTA, which is typically used to return data such as ack:0x84 from slave.

5. Timing Requirements

Several timing of the HS mode is important when debugging DSI or CSI: T_lpx,t_hs-settle≈t_hs-prepare + t_hs-zero,t_hs-trail, which generally follows the following principles: Host-Side T_hs-settl E > Slave end of T_hs-settle.

Second, DSI

1. Line composition

1 clock lines and 1 to 4 data cables are required in DSI.

2, two kinds of interface LCD

* Comman mode (corresponding MPU interface)

* Video mode (corresponding to RGB interface)

Video data can only be transmitted via HS mode in this mode.

3. Packet type

Short Package : 4 bytes, consisting of 3 parts:

* Data Identifier (DI) * 1byte:contains the Virtual channel[7:6] and data type[5:0].

* Packet Data * 2byte:length is fixed at the bytes

* Error Correction Code (ECC) * 1byte:allows single-bit errors to being corrected and 2-bit errors to be detected.

Long Bag : 6 ~ 65541 bytes, also made up of 3 parts:

* Packet Header (4 bytes)-Baotou

Data Identifier (DI) * 1byte:contains the Virtual channel[7:6] and data type[5:0].
Word Count (WC) * 2byte:defines the number of bytes in the Data Payload.
Error Correction Code (ECC) * 1byte:allows single-bit errors to being corrected and 2-bit errors to be detected.

* Data Payload (0~65535 bytes)-Valid
Length = Wcxbytes

* Packet Footer (2 bytes): Checksum-End of package
If the payload has length 0 and then the Checksum calculation results in FFFFh
If the Checksum isn ' t calculated, the Checksum value is 0000h

4 . Package type sent from controller to peripheral

If you want to read the data or state from the peripheral, you will also need to send the BTA command after the processor has sent the Read command, and the non-read command will return trigger message 0x84After the peripheral is successfully received.

5. from peripheral to processor packet type

The returned data is generally divided into 4 types:

* Tearing Effect (TE): Trigger Message (BAH)
* Acknowledge:trigger message (84h)
* Acknowledge and Error Report:short packet (Data Type is 02h)
* Response to Read request:short packet or long packet
Generic read Response, DCS read Response (1byte, 2byte, multi byte)

The read data Return value Resolution example is as follows:

[CPP]View Plaincopy

2. -Acknowledge and error report (if Error occurs)
4. Byte 0 is 0x87 (escape mode low power data transmission header)
6. Byte 1 is 0x02 (Data type, 8.10 of ' MIPI Alliance specification for DSI ')
8. Byte 3,2 is error report bits[15:0] (8.9.5 of "MIPI Alliance specification for DSI")
10. Byte 4 is the ECC, calculated from byte
14. -Generic Short READ response
16. Byte 0 is 0x87 (escape mode low power data transmission header)
18. Byte 1 is 0x11 or 0x12 (8.10 of "MIPI Alliance specification for DSI")
20. Byte 2,3 is the read data. If only 1 bytes is returned, Byte 3 would be 0x00
22. Byte 4 is the ECC, calculated from byte
26. -Long READ Packet response
28. Byte 0 is 0x87 (escape mode low power data transmission header)
30. Byte 1 is 0x1A (8.10 of "MIPI Alliance specification for DSI")
32. Byte 3,2 is the word Count N (n=0 to 65535)
34. Byte 4 is the ECC, calculated from byte
36. Byte 5 to Byte 5+n-1 is the N-byte read data
38. Byte 5+n+1, byte 5+n is the checksum, calculated on byte 5 to byte 5+n-1. If
40. Checksum is isn't calculated by peripheral, this field is 0x0000.

6.3 Kinds of data formats in Video mode

* Non-burst Mode with Sync pulses
* Non-burst Mode with Sync Events
* Burst Mode

* Debug Record

LCD Side splash screen problem, the original information: analysis of the system board sent video mode timing, a summary of the following

Hsclk:160mhz
Per Lane bit-rate:320mbps (UI=3.125NS)
HS SoT Hs-prepare + hs-zero approx. 155ns

The timing is suspected by the above, because the IC HS data settle timing
It appears that our output of the MIPI signal Hs-prepare + Hs-zero is shorter than the LCD default setting. There are random full screen flashing problems by adjusting the value of VFP and VBP to the ideal state. In addition, the LCD VCC after the use of MOS control after sleep will have a 2.0V suspension voltage, through the RC circuit will be the voltage off, the C78 replaced by a 10K resistor.
There are several more important voltages on the LCD circuit: AVDD, VCC, VGH, VGL, HAVDD, VCOM (obtained by the AVDD by a resistive divider)

* Wake-up slow problem

In the initial debugging of several LCD inside the initialization of the CMD is relatively small, and later in the debugging of an IPS screen when the wake up to 3 seconds, this LCD initialization cmd has more than 100, before the commissioning of an LCD when each CMD sent after a delay of 10ms to send A cmd, so in this LCD can not have delay, and after debugging in order to ensure the success of sending the LP transmission speed increased by 3 times times (here need to read the return value of each CMD 0x84 to confirm that the command is sent successfully), the optimized wake-up time of less than 1 seconds.

* LCD Parameter Understanding correction

Only to find that the LCD has been several parameters HFP, HBP, VFP, VBP understand the error, the correct should be based on synchronous signal (HSYNC, VSYNC) as the benchmark, before the synchronization signal called Front, after the synchronization signal called back, Rather than the previous understanding of effective pixels as the benchmark.

* LCD Display has a jagged-like problem

These two days (12.11) also debug a 540 x 960 resolution of the MIPI LCD, at the beginning of the time is not lit, and the supplier confirmed that the initialization code is wrong, and the correct initialization code can be lit, but the display of the image is jagged, That is, there is no alignment. Before the other platform has encountered a similar problem, that is, the resolution is not an integer multiple of 16, the LCD controller when fetching data will be misaligned.  Side study datasheet and ASIC colleagues discussed, and later identified a scheme: the DSI, LCD registers set the resolution of 540 X 960 to allow the LCD to correctly identify the signal, but framebuffer need to be set to 544 x 960 to align, and set The Source pitch register is 544, so the display is normal, the equivalent of framebuffer in each row of the last 4 pixel will be lost by the LCD controller.

Today (12.12) in the discussion with the ASIC colleague corrected the previous understanding: When the LCD Controller calculates the data, the address is calculated according to the (x, y) coordinates, which is approximately address = y * pitch + x + Base,pitch is a row of pix The size of the El in memory, this is at least aligned to 8byte, because the bus width is 8byte, as described in Data sheet "Source pitch for RGB channel, QWORD aligned if linear mode “。 The formula for calculating the pitch value before is: XRES/8 * bits_per_pixel/8, if xres = 540,bits_per_pixel = 32, the result of the calculation is because the rounding is 0x10c, actually the correct value should be 0x10e, so need Change the formula to: Xres * (BITS_PER_PIXEL/8)/8, that is, if the xres is an even number in the case of 4byte per pixel, you can meet the alignment requirements without changing to 544.

MIPI Commissioning Experience