MIPI DSI and d-phy initialization sequence

MIPI DSI and D-PHY Initialization Sequence -- A- inShenzhen Nanshan Ping Shan Village Zengjianfeng Reference Document: I. mx 6Dual/6Quad Multimedia Applications Processor Reference Manual43.4Programming43.4.1DSI and D-PHY Initialization Sequence43.4.1DSI and D-PHY Initialization Sequence This chapter describes the procedure forDSI and d-phy initialization. This process isBased on APB RegisterInterfaceaccess. This chapter describes the DSi and D-the process of PHY initialization.        The process is accessed based on the APB registration interface. bydefaultRegister PHY_RSTZ isActivating the PHY resets Physhutdownz, PHYRSTZ and disabling ENABLECLK and register phy_test_ctrl0 isBydefaultAsserting the TESTCLR pin. All the PHY reset pins is being activated bydefault. By default, the PHY_RSTZ register has reset PHY Physhutdownz,phyrstz and disabled ENABLECLK, and the register phy_test_ctrl0 is turned off by default for TESTCLR pins.            All PHY Resset pins are activated by default. +---------------------------------------------------------------+            |            Mipi_dsi_phy_rstz Field Descriptions | +---------------+-----------------------------------------------+            | Field |             Description | +---------------+-----------------------------------------------+            | to–3|             |   | -           |             Reserved | +---------------+-----------------------------------------------+            |2|             | | PHY_ENABLECLK | Enables D-phy Clock Lane Module when1| +---------------+-----------------------------------------------+            |1| D-phy Reset Disable when1, used to place the | | Phy_rstz | Digital section of D-phyinchReset State | +---------------+-----------------------------------------------+            |0| D-phy Shutdown Disable when1, Used to place | | Phy_shutdownz | The complete D-phy macroinchPower Down | +---------------+-----------------------------------------------+Configure Register phy_if_cfg with correct, the number of lanes to being used by the controller.            Configure the number of lane for the controller by configuring the PHY_IF_CFG register. +-------------------------------------------------------------------+            |            Mipi_dsi_phy_if_cfg_ Field Descriptions |   +----------------+--------------------------------------------------+            |                    Field |            Description | +----------------+--------------------------------------------------+            | to–Ten|             |      | -         |             Reserved | +----------------+--------------------------------------------------+            |9–2|             Configures minimum wait period to request an HS | | Phy_stop_wait_ | Transmission after the stop state accountedinch|      | Time |             Clock Lane Cycles | +----------------+--------------------------------------------------+            |1–0|                     Number of active data lanes.             |    | N_lanes |xx 1Data Lane (Lane0)                          |                | | on 2Data Lanes (Lane0, and1)                  |                | |Ten 3Data Lanes (Lane0,1and2)                 |                | | One 4Data Lanes (All) | +----------------+--------------------------------------------------+Configure the Tx_esc clock frequency to a frequency lower than 20MHz isThe maximum allowed frequency forD-phy ESCAPE mode. This isDone by writinginchRegister clkmgr_cfg, Field tx_esc_clk_division. Tx_esc_clk_division divides Byte clock and generates a TX_ESC Clock forThe d-phy. (Note:byte clock isLimited to 125MHz (1ghz/8bits) and by writing tx_esc_clk_division=0x07Tx_esc clock would always lower than 20MHz) configuration Tx_esc clock frequency less than 20MHz to D-phy escape mode, configured by the tx_esc_clk_division to the CLKMGR_CFG register. Tx_esc_clk_division divides the byte clock and generates a TX_ESC clock to d-phy. (Note: Byte clock is limited to 125MHz (1ghz/8bit), and to tx_esc_clk_division=0x07Tx_esc clock will always be less than 20MHz)+-------------------------------------------------------------------+            |            Mipi_dsi_clkmgr_cfg Field Descriptions |   +-------------+-----------------------------------------------------+            |   Field |             Description | +-------------+-----------------------------------------------------+            | to– -|             |     | -       |             Reserved | +-------------+-----------------------------------------------------+            | the–8| Division Factor forTime Out clock used asTiming | | To_clk_ | UnitinchThe configuration of HS to LP and LP to HS | | dividsion |                                   Transition error.             | +-------------+-----------------------------------------------------+            |7–0| Division Factor forTX ESCAPE Clock Source (| | Tx_esc_clk_ | LANEBYTECLK pin), values0and1Stop Tx_esc | | dividsion |                                   Clock generation.             | +-------------+-----------------------------------------------------+Configure the dphy PLL clock frequency through the TEST Interface to operate in 1GHz, assuming that the ref_ CLK isprovided with a frequency of 27MHz assumes the 27MHz frequency provided by the REF_CLK, the dphy PLL clock frequency is configured to 1GHz by the test interface operation. +---------------------------------------------------------------------------+            |            Mipi_dsi_phy_tst_ctrl0 Field Descriptions |   +-------------+-------------------------------------------------------------+            | Field |             Description | +-------------+-------------------------------------------------------------+            | to–2|             |      | -      |             Reserved | +-------------+-------------------------------------------------------------+            |1| PHY TestInterfaceStrobe signal.             Used to clock Testdin bus | | PHY_TESTCLK | Into the d-phy.             In conjunction with Testen signal Controls |             | |             The Operation selection | +-------------+-------------------------------------------------------------+            |0| PHY TestInterfaceClear.             When active performs vendor | | PHY_TESTCLR | SpecificInterfaceInitialization (Active high) | +-------------+-------------------------------------------------------------+            +--------------------------------                --------------------------------------------------+            |            Mipi_dsi_phy_tst_ctrl1 Field Descriptions |    +--------------+-------------------------------------------------------------------+            | Field |             Description | +--------------+-------------------------------------------------------------------+            | to– -|             |     | -        |             Reserved | +--------------+-------------------------------------------------------------------+            | -| PHY TestInterfaceOperation Selector:when1Configures Address | | Phy_testen | Write operation on the falling edge of TESTCLK; When0Configures |              | |             A data write operation on the rising edge of TESTCLK | +--------------+-------------------------------------------------------------------+            | the–8| PHY output8-bit Data Bus forRead-back andInternalProbing | | Phy_testdout |             Functionalities | +--------------+-------------------------------------------------------------------+            |7–0| PHY TestInterfaceInput8-bit Data Bus for InternalRegister | | Phy_testdin |             Programming and test Functionalities access | +--------------+-------------------------------------------------------------------+Write @ phy_tst_ctrl0- +'h00000000 This disables the TESTCLR pin enabling the interface-write new values to the Dphy internal REGISTERS.Write to Phy_tst_ctrl0 32'h00000000, disables the TESTCLR pin while enabling the interface to write values to the dphy internal registerWrite @ phy_tst_ctrl1- +'h00010044 This enables the testen pin bit , the this Core register and configures the Testdatain to 8'H44. This operation initiate the configuration process of the test code number0x44. Write to Phy_tst_ctrl1'h00010044, enable Testen pin core Register 17 bit, and configure Testdatain value to 8'H44, this operation starts the configuration test code number0x44. Write @ phy_test_ctrl0- +'h0000002 followed by a new write to phy_test_ctrl0-32'h00000000. This operation toggles the TESTCLK (bit2) and the Testdin would be sampled on the falling edge of TESTCLK latching aNewtest Code. Write to Phy_tst_ctrl0'h00000002 is always followed by writing to Phy_tst_ctrl0'after h00000000, this operation triggers TESTCLK (BIT2) and generates a new TEST code write with the Testddatain data sampled (PHY_TEST_CTRL1)- +'h00000074 Disabling the testen pin and configuring Testdatain to 8'H74. This operation prepares theInterfaceTo loadinchTest code0x44The0x74value. Write @ phy_test_ctrl0- +'h00000002 followed by a new write to phy_test_ctrl0-32'h00000000. This operation toggles the TESTCLK and the Testdin would be sampled on the rising edge of TESTCLK latching aNewcontent data to the configured test code. Write @ phy_rstz- +'h00000007. This operation asserts Physhutdownz, Phyrstz and Enableclk releasing the PHY from power down. The PHY would startup the PLL locking procedure to 1GHz operation.Write to Phy_rstz 32'h00000007 This operation interrupts the PHYSHUTDOWNZ, Phyrstz and enable clocks, allowing PHY to resume from the power-off state, and PHY will restart the PLL lock to 1GHz operation. Read @ phy_status- +'hxxxxxxx1, until bit 0 Phylock is detected at 1 signaling the PLL is locked and the a stable byte clock is being pro Vided to the DSI host controller.Read the value of Phy_status 32'The hxxxxxxx1, until the bit 0 bits of the register is checked to 1, indicates that the PLL is locked and that it can be supplied to the DSI host controller in a stable byte clockRead @ phy_status- +'hxxxxx1x1, until bit 2 Phystopstateclklane is read'1'identifying that Clock Lane was in Stop state. Clock Lane need to IS in Stop state so, the d-phy can switch to other operational states such as the high speed mode.< /c0>Read the value of Phy_status 32'hxxxxx1x1, until the bit 2 bit of the register is checked to 1, determine the clock lane in the stop state. Clock Lane needs to enter the stop state so that the d-phy can switch to other operating states, such as high speed mode. Write register Phy_if_ctrl bit0To generate high speed clock (TXREQUESTHSCLK).        To Phy_if_ctrl, bit 0 is written to 1, which generates high speed clock (TXREQUESTHSCLK). only after:1) PLL locked and2) Clock LaneinchStop-state; The PHY would drive the correct LP sequence to configure the receiver end forHS. Continue to run only under the following conditions:1. The PLL is locked;2. Clock Lane enters stop-state, PHY will drive the correct LP sequence to be configured from the device and into the HS state. • D-PHY starts transmitting HS clock on the clock Lane. D-phy began to transmit HS clock above the clock lane.

MIPI DSI and d-phy initialization sequence