MiS603 Development Board 1.4 Building Engineering and its simulation-led

MiS603 Development Team

Date: 20150911

Company: Nanjing mi Lian Electronic Technology Co., Ltd.

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Website: www.milinker.com

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1.4 Establishment of engineering and its simulation-led

In this section, we formally establish the ISE project, and learn Modelsim simulation, which is also a basic step in the project, in the following chapters will be introduced.

1.4.1 Ise Project established

STEP1: Start à all Programs àxilinx design toolsàise design Suite 14.7àise design toolsàproject Navigator, open Ise software, or open from desktop shortcut. Click New Project to create the project, name the project led, and store it in the E:\Xilinx_Prj\demo_v\led folder and click Next. Good friends in English you can click More info to see the English instructions for key building projects.

STEP2: Genie 3 is the SPARTEN6 series FPGA, select the information in the red box. wherein the synthesis tool chooses XST, which is the ISE comes with the integrated device, simulator chooses Modelsim-se Mixed, supports Verilog and VHDL language emulation, as shown in, click Next.

STEP3: The next interface is an overview of engineering information, so you can look at the finish.

STEP4: Select Projectànew Source., the following interface appears, select Verilog Module, project name is Led_top, click Next.

STEP5: Next appears the interface, enter the information in the Red box, click Next.

STEP6: This interface is a summary of the input and output signals of the led_top, click Finish.

STEP7: Enter the following in the led_top.m file. It is recommended to write it yourself once, and direct replication may have errors. After writing it as shown.

1. ' Timescale 1ns/1ps

2./*

3. * FILE:LED_TOP.M

4. * Description:this is led test file.

5. * Author:sanliuyaoling.

6. * Copyright:

7. *

8. * History

9.----------------------------

* rev:0.00

* data:06/08/2015

12. *

* Create.

----------------------------

15. */

Module Led_top (

. Input SYS_CLK,//system clock 50MHz

Input Sys_rst_n,//global system reset:active Low

Output LED//led output signal

20.);

21st.

//download Hardware Use

//parameter dly_cnt = "d25000000";

//parameter half_dly_cnt = "d12500000";

25.

//modelsim use

Parameter dly_cnt = "d20";

Parameter half_dly_cnt = "D10";

29.

. reg R_led;

. reg [24:0]count;

32.

//counter Control

[Email protected] (Posedge sys_clk or Negedge sys_rst_n)

. Begin

if (!sys_rst_n)

Panax Notoginseng. Begin

. Count <= ' D0;

. end

. else if (count = = dly_cnt)

A. Begin

Count <= ' D0;

. end

. else

"Begin"

Count <= count+25 ' D1;

A. End

. end

49.

//led Output Register Control

[Email protected] (Posedge sys_clk or Negedge sys_rst_n)

A. Begin

if (!sys_rst_n)

A. Begin

r_led <= 1 ' b0;

. end

. else if (Count < half_dly_cnt)

"Begin"

r_led <= 1 ' B1;

End

. else

A. Begin

r_led <= 1 ' b0;

. end

End

assign led = r_led;

Endmodule.

1.4.2 Modelsim Simulation

Before we perform the Modelsim simulation, we need to write an incentive file called Test Bench. Next we write this file.

STEP1: Select Projectànew Source., the following interface appears, select Verilog Test Fixture, the file name is tb_led, click Next.

STEP2: After the following screen appears, click Next.

STEP3: After that, the following summary interface appears, click Finish.

STEP4: Write Test Bench, just add a few lines in the TB_LED.V, as shown, add content is 4 inside the content. Then switch the interface to 1 and double-click the simulate behavioral Model.

STEP5: After Ise calls Modelsim emulation, click 1, first 2 waveform, simulation succeeded. Haha ^_^.

MiS603 Development Board 1.4 Building Engineering and its simulation-led