MiS603 Development Board 17th HDMI Interface Test Input log Header

MiS603 Development Team

Date: 20150911

Company: Nanjing mi Lian Electronic Technology Co., Ltd.

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MiS603 Development Board 17th HDMI Interface Test 17.1 HDMI overview

HDMI is the abbreviation for High Definition multimedia interface, also known as the Hi-Res multimedia interface, a digital video/audio transmission technology, a dedicated digital interface for image transmission, when transmitting video and audio, The maximum data transfer speed is 2.25gb/s. Note here that HDMI transmits digital signals, and the VGA transmits analog signals, which is one of the biggest differences between the two.

HDMI system architecture has 2 parts, they are transmitting source and receiver, so a device with an HDMI interface may have one or more transmitters or receivers, HDMI input to meet the HDMI receiving rules. As shown, the transmitter and receiver of HDMI is connected with four pairs of differential signals, including three pairs of data and a pair of clocks, the data channel is used to transmit video, audio and some auxiliary information, a pair of clocks is usually equal to the bitrate of the video pixels, sent through a pair of clock channels. The receiving end obtains three data from the data channel via this pair of clocks, and references the HDMI manual for additional details about HDMI.

Next introduce the HDMI interface, HDMI interface is mainly divided into Class A, Class B and Class C, where a-type interface is mainly used in consumer electronics applications, but also the most common, a total of 19 pins, as shown, the following table is the corresponding pin description. Class B has a group of signals, which is designed to transmit ultra-high-definition images with a large size and a total of 29 pins. C analogy is small, mainly used in portable devices.

HDMI Class A interface description

PIN number	Description	PIN number	Description
1	TMDS data	11	TMDs Clock Shielding
2	TMDS Data 2 Masking	12	TMDs Clock-
3	TMDS Data 2-	13	Cec
4	TMDS Data 1+	14	Keep
5	TMDS Data 1 Masking	15	Scl
6	TMDS Data 1-	16	Sda
7	TMDS Data 0+	17	DDC/CEC Ground
8	TMDS Data 0 Masking	18	+ +
9	TMDS Data 0-	19	Hot-swap detection
10	TMDs Clock +

17.2 HDMI hardware circuit analysis

This design uses the dedicated HDMI transmitter chip SIL9134, the highest support [email protected] Video input, support 3D output. Since the SIL9134 requires internal register initialization prior to use, the configuration process is complex and the board is equipped with a STM32 chip to configure the SIL9134.

As shown, the input data is SIL9134 encoded into an HDMI video stream, the video data and control signals are connected to the FPGA, and the configuration port is connected to the STM32. Because the FPGA pin is limited, the MIS603 does not bring out the audio interface, and the subsequent development platform will improve this function. The SIL9134 and FPGA, STM32 connection modes are as follows.

SIL9134 and FPGA connection modes

Label	The corresponding FPGA pin	Describe
Video_clk	N8	Drive clock, output by FPGA
Video_blank	R9	Data valid, output by FPGA
Video_hs	P9	HDMI line sync signal, output by FPGA
Video_vs	N9	HDMI field sync signal, output by FPGA
VIDEO_D[23:0]	H13,j14,k15,l14,m15,n14,p15,r15,j13,l12,m13,r14,j11,k12,t14,r12,m12,p12,n12,p11,n11,m10,l10,t9	HDMI data bits, support YUV444, RGB888 input

Note: The VGA and HDMI are shared with the FPGA pins.

SIL9134 and STM32 Connection modes

Label	The corresponding STM32 pin	Describe
9134_reset	PA2	SIL9134 Reset PIN, low active
Scl	PC9	I²c Bus Clock
Sda	PC8	I²c Bus Data

Note: Due to SIL9134 internal register extra 255, a SIL9134 chip corresponds to 2 device address, device 1 of the I²c address: 0X72, device 2 of the I²c address: 0X7A.

For 1080P video clock 148.5MHz, the hardware requirements are high, PCB must be long wiring.

For HDMI interface, differential signal transmission, PCB must be long wiring.

17.3 HDMI Chip Register Configuration

There are many registers inside the SIL9134, here are a few common registers and their meanings, please refer to the SIL9134 Programming Manual for more information.

Device ID Register:

For SIL9134 Device ID is 0x9134,sil9034 device ID is 0x9034, by reading the device ID can determine whether the I²c bus is working properly.

Device Control Register 1:

BIT6: The state of the external input pin vsync.

Bit5:vsync enabled, configured to 1.

Bit4:hsync enabled, configured to 1.

Bit2: Input bus Select, configured to 1, select 24-bit bus mode.

Bit1: Edge selection, configured to 0, falling edge latch input signal.

Bit0: Power-down mode, configured to 1, normal operation mode.

In summary, this register configuration value is 0x35.

Video Mode Register:

BIT7-6: Select the number of bits per video output channel, configured to 00.

BIT5: configured to 0, not enabled.

BIT4: configured to 0, data 16-235 does not become 0-255.

BIT3: Configured to 0,YCBCR does not convert to RGB, that is, the input RGB signal.

BIT2: configured to 0, do not enable 4:2:2 on the sample to become 4:4:4.

BIT1: configured to 0, not enabled.

BIT0: Configured to 0, does not extract the sync signal.

In summary, this register is configured to 0x00, mainly RGB input RGB output, the HDMI is configured for DVI compatibility mode.

The SIL9134 is configured with an internal register via the I²c interface, as shown in the read and write timing.

Note: S = start, starting signal Sr = Restart, start signal restart

As = slave acknowledge, slave answer Am = Master Acknowledge, host answer

N = no ack, no answer P = stop, stop

w/r= read-Write Select bit

SIL9134 chip Configuration Interface Timing

From the reading sequence can be seen, send S signal, slave address +w signal, as signal, device internal offset address, as signal, device address +r signal, as signal, read data 0, AM signal .... As signal, p signal. Write sequence can be seen, send S signal, slave address +w signal, as signal, device internal offset address, as signal, write data 0, as signal .... As signal, write data n, p signal.

SIL9134 Address Select pin CI2CA connection GND, address selection as shown, Address: 0x72 and 0x7a.

For detailed code on STM32 configuration SIL9134, refer to the accompanying configuration file, which is not explained here. The rest of the configuration information references the STM32 code.

17.4 HDMI Timing Analysis

The SIL9134 works in DVI mode with the same working timing and VGA, with reference to the VGA part timing analysis.

17.5 HDMI Timing Simulation

The SIL9134 works in DVI mode with the same working timing and VGA, with reference to the VGA part timing simulation.

17.6 Chipscope Data analysis

Take 720P (1280x720) as an example to grab data analysis. Sampling Clock hdmi_clk_o.

Line sync signal: Starting at 1649, 3299 ends with a total of 1650 pixel points,

8 color bars correspond to the data.

17.7 program Analysis

The SIL9134 is configured in a DVI-compatible mode, which is simple to enter RGB888 data directly, with the same timing and VGA timing, and the same code as the VGA section.

1:HDMI time series parameter definition file, support different resolution, only need to change the macro definition can be implemented.

2:HDMI test the top-level file, and instantiate the DCM Clock module and the Hdmi_driver module.

3: Generates 74.25MHZ clock module by 50MHz, some deviations.

4:hdmi_driver module to generate the relevant HDMI timing parameters.

5:chipscope module, online analysis of data.

6:UCF files, including pin assignment and clock constraints.

17.8 Program source code

Detailed reference:

6_03_mis603_x25_hdmi_test_720p:720p test, resolution 1280x720.

6_03_mis603_x25_hdmi_test_1080p:1080p test, resolution 1920x1080.

Note: The test is using HDMI to VGA test, note the monitor resolution is supported.

720P test Results

1080P test Results

17.9 Summary

Understand the basic knowledge of HDMI transmission, IIC protocol, SIL9134 DVI configuration.

MiS603 Development Board 17th HDMI Interface Test Input log Header