Remember the "MiZ702 study notes"--pure PL VGA Drive This article, with Verilog wrote a VGA driver. What we are going to introduce today is to package this project into an ordinary IP, which is intended to pave the way for a later article.
For the purpose of packaging a common IP, you can paste this IP directly into the block file. (and instantiation with text is a meaning). Should be for us to call the zynq of the nuclear time is generally used in the form of block, in order to ZYNQ and our VGA module more convenient organization, we need this IP packaging method.
Why is the emphasis on the ordinary IP, the idea is to differentiate the IP with Axi interface, this is described in the following.
This packaging process is very simple, after creating a Vivado project, prepare our VGA Verilog source file:
I will be in these files, under the current project under the song folder standby. Then select Tools Create and Package IP:
Click Next:
Select the IP in the form of the following tag:
Next is the key step, select the location of the source file that we just prepared, and click Next:
Continue Next:
Finally Click Finish:
After clicking Finish, a new project is automatically created specifically for this IP project. Notice in the red box, there is a Name property, here his name is your top-level file name plus a version number, the software automatically to you fill in, remember the name, and then add the IP, is based on the name to find our IP.
There is a warning, do not bother him not to affect, we directly pack:
Press the package IP to complete the packaging, the project is automatically closed, back to my first new project, you can add our packaged IP.
First create a block, and then select the Add IP, search for the top-level file name, you can find it ~ ~
By double-clicking it, you can add it to the block file:
This kind of graphical instantiation and text instantiation, we all need to skillfully use, today is here.
MiZ702 Learning Note 12--Package a normal VGA IP