MMU Management Mechanism

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MMU: Memory Management Unit

*Ing between virtual memory space and physical storage space. Page-based virtual memory management is adopted in arm. It divides the virtual address space into blocks of fixed size, each of which is called a page, and the address space of physical memory is also divided into pages of the same size. The page size can be divided into coarse-grained and fine-grained. MMU converts virtual addresses to physical addresses.

* Control of memory access permissions.

* Set the buffering feature of a virtual bucket.

MMU can lock some address translation entries in TLB (translation lookaside buffer) to store address translation entries queried in the page table from virtual addresses to physical addresses ), in this way, the address translation speed related to the address translation entry remains fast. In MMU, register C10 is used to control the Lock of TBL content.

MMU can divide the entire bucket into a maximum of 16 domains ). Each domain corresponds to a certain memory area, which has the same access control attributes. Register C3 in MMU is used to control the attribute configuration related to the domain.

Table 1Registers related to MMU operations

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Memory Function

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Some BITs in register c1 are used to configure some MMU operations.

Register C2 stores the base address of the page table in memory

Register C3 sets domain access control attributes

Register C4 reserved (resvered)

Register C5 memory access failure status indication

Address when access to register C6 memory fails

Register C7

Register C8 controls operations related to clearing TLB content

Register C9

Register C10 controls operations related to locking TLB content

++ ++

When c1 [0] of the CP15 register is set to 0, MMU is forbidden. When it is set to 1, enable MMU, for example:

MRC P15, 0, R0, C1, 0, 0; transmitted from C1 of the coprocessor CP15 to the ARM processor R0

ORR r0, #01; write 1 to the co15 register c1 [0]

MCR P15, 0, R0, C1, 0, 0;

1. Structure: The structure of the MMU memory system allows fine-grained control over the memory system. Most of the control details are provided by the conversion table in the memory. The entry of these tables defines the attributes of various memory areas from 1 kb to 1 MB. These attributes include: Ing virtual addresses to physical addressesThe address generated by the ARM processor is called a virtual address. MMU allows ing this virtual address to a different physical address. This physical address represents the location of the accessed primary storage. If fast context switch extension is used, the virtual address in this article should be the modified virtual address (modified virtualaddress) this method allows us to manage the locations of physical memory in many ways, for example, allocating memory for different processes by ing addresses with potential conflicts; allow applications with Discontinuous addresses to map them to contiguous address spaces. Ø Memory Access permission (permissions)Control the access, read-only, and read/write permissions of the storage area. When you access a memory that cannot be accessed, an exception occurs to the ARM processor. The permission is affected by whether the program is running in the user or privileged State, and whether the domain is used. Ø Cachability and bufferability bits [C and B]These System Control coprocessor registers allow advanced control over the system in the cache and buffer section, such as the position of the conversion table. They are also used to provide arm with Memory exception status information. The process of searching the entire conversion table is called traversing the conversion table. It is implemented by the hardware brake and requires a lot of execution time (at least one memory access, usually two ). To reduce the average consumption of memory access, the conversion table traversal results are cached in one or more structures called translation lookaside buffers (tlbs. Generally, in the implementation of arm, each memory interface has a TLB. · A system with a memory interface usually has a unique TLB. A system with a separate command and a data memory interface usually has a separate command TLB and a data TLB. If the system has a high-speed cache, the number of caches is usually determined by the same method. Therefore, in a high-speed cache system, each high-speed cache has a TLB. When the conversion table in the memory is changed or different conversion tables are selected (by writing register 2 of CP15), the previously cached conversion table traversal results will no longer be valid. The MMU structure allows you to refresh the TLB. The MMU structure also allows specific conversion table traversal results to be locked in a TLB, which ensures that access to the relevant storage area will never lead to conversion table traversal, this also benefits Real-Time Code that locks commands and data in the cache. 2. Memory Access sequence when the arm wants to access the memory, MMU first looks for the virtual address table in TLB. If the arm structure supports separate addresses TLB and instructions TLB, it uses: · use commands to access TLB. Use Data TLB for all other access categories. If TLB does not have a virtual address entry, the conversion table traversal hardware obtains the conversion and access permissions from the conversion table in the primary storage. Once obtained, the information will be placed in TLB, it will be placed in an unused entrance or overwrite an existing entrance. For information about the conversion table and the implementation of the conversion table traversal, see the conversion process section. Once obtained for the TLB entry accessed by the memory, the information will be used: 1. the C (high-speed cache) and B (buffer) bits are used to control the high-speed cache and write buffer, and determine whether the high-speed cache is used. (If there is no cache or write buffer in the system, the corresponding bit will be ignored) 2. access permission and domain bit are used to control whether access is allowed. If not, MMU sends a Memory exception to the ARM processor; otherwise, access is allowed. Detailed descriptions of access permissions, domains, and exceptions are provided. 3. For a system without high-speed cache (including access to all memory in the system without high-speed cache), the physical address will be used as the primary memory access address. For a system with a high-speed cache, if the high-speed cache is not selected, the physical address will be used as the line fetch address. If the cache is selected, the physical address is ignored. Figure 3-1 shows that the high-speed cache system 2.1 allows and disables MMU by writing the system to control the 0th-bit register 1 of the coprocessor to allow and disable MMU. After resetting, this is 0 and MMU is disabled. When an MMU is disabled, memory access is processed as follows: 1. Determine whether high-speed cache and write buffer can be allowed when the MMU is disabled. · When the MMU cannot allow high-speed cache and write buffer, the C and B BITs do not work. · When MMU is disabled, high-speed cache and write buffer are allowed: I. when accessing data, it is considered that there is no cache or write buffer (C = 0, B = 0) II. when the command is executed: a) when the system has only one unique TLB, it is considered that there is no high-speed cache. (C = 0) B) when the system only has an independent command TLB, it is considered to have a high-speed cache. (C = 1) 2. Check if you do not have the access permission to the memory, and the MMU does not generate any abnormal signals. 3. The physical address is the same as the virtual address (the so-called flat address ing mode ). Before MMU is allowed, An appropriate conversion table must be created in the memory and all related CP15 registers must be initialized correctly.Allow and disable MMU to directly change the ing between virtual addresses and physical addresses (unless the conversion table is set to flat address ing mode ). Therefore, when MMU is allowed, all the cache needs to be refreshed. In addition, if the physical address and virtual address of the MMU command are allowed to be different, obtaining the command will become complicated. Therefore, it is strongly recommended that MMU commands have the same physical address and virtual address. 3. MMU supports node-or page-based memory access during the conversion process: Section(Section) memory blocks of 1 MB support different page sizes of 3: MICRO PAGE(Tiny page) constitutes a 1 kb memory block Small page(Small page) constitute a memory block of 4 kb Large page(Large page) a 64 kB memory block section and a large page support ing a large memory range with only one TLB entry. Small pages and large pages have additional access control: Small pages are divided into 1 kb subpages, and large pages are divided into 16 KB subpages. There are no sub-pages on a micro-page, and the access control to the micro-page is for the whole page. There are two conversion tables in the primary storage: Level 1 TableStorage section conversion table and pointer to second-level table. Level 2 TableStores the conversion tables of large and small pages. A type of second-level table stores micro-page conversion tables. MMU converts the virtual address generated by the CPU into a physical address to access external memory, and inherits and checks the access permission. There are four paths for address translation. The path selection is determined by whether the address is marked as "segment ing access" or "Page ing access. Page ing access can be large, small, and micro-page access. However, the conversion process always starts from the first-level table as described below. Only the first-level table needs to be read for access to page ing, and the second-level table needs to be read for access to page ing. 3.1 The conversion table base address when the on-chip TLB does not contain the required virtual address entry, the conversion process is started. The base address register of the conversion table (register 2 of CP15) stores the physical address of the base address of the first-level conversion table. Only bits [31: 14] is valid. Bits [] should be zero (sbz ). Therefore, the first-level table must be at 16 kb. .3.2 take the bits [31: 14] of the base address register of the first-level table to form a 32 physical address connected to the virtual address bits [31: 20] and two 0-bit connections, 3-2. This address selects a four-byte conversion table entry, which is the first level descriptor or pointer to the second level page table. 3.3 each entry of the first-level descriptor level-1 table is a descriptor that describes how the 1 MB virtual address associated with it maps. See table 3-1. According to the combination of BITs [1:0], there are four possibilities: If bits [1:0] = 0b00, the associated address is not mapped, attempting to access them will generate a conversion error (fault ). Because they are ignored by hardware, the software can use the bits [31: 2] of such descriptors for its own purposes. We recommend that you maintain the correct access permission for the descriptor. · If bits [1:0] = 0b10, this entry is the section descriptor of the associated address. For details, see the descriptor and conversion section. · If bits [0] = 1, this entry provides a rough second-level table (bit [1] = 0 ), or a detailed second-level table (bit [1] = 1 ). Each type of table describes the ing of the 1 MB Storage area associated with it. The rough second-level table is small. Each table is 1 kb, and each detailed second-level table is 4 kb. However, a rough second-level table can only map large pages and small pages. A fine second-level table can map large pages, small pages, and micro pages. Section 3 Descriptor and conversion referencesIf the first-level descriptor is a section descriptor, each field has the following meanings: bits [1:0] descriptor type identifier (0b10 indicates the section descriptor) bits [] cache and buffer bits [4] are defined by specific implementations. Bits [] is not currently in use in one of the 16 domains in this descriptor Control Section, it should be zero bits [] Access Control. See table 3-3 bits [] which is not currently in use. It should be zero base address of section bits [31: 20, A 12-bit high bitmap with a physical address 3-3 represents the complete process of segment conversion. Note: --------------- the access permission must be checked before the physical address is generated. For the order of access permissions, see the access permission section. --------------------- 3.5 rough page table DescriptorIf the first level descriptor is a rough page table descriptor, each field has the following meanings: bits [1:0] descriptor type identifier (0b01 indicates a rough page table descriptor) bits [] is defined by the specific implementation. Bits [] one of the 16 domains on the page controlled by this descriptor is not used now. It should be zero bits [31: 10] The base address of a page table is a pointer to the second base table, which provides the base address for accessing the second base table. The level-2 rough page table must be aligned at the 1kb boundary. If the level 1 reads the Level 2 rough page table descriptor, the level 2 descriptor is read as shown in Figure 3-4. 3.6 fine page table DescriptorIf the first level descriptor is a fine page table descriptor, each field has the following meanings: bits [1:0] descriptor type identifier (0b11 indicates a fine page table descriptor) bits [] is defined by the specific implementation. Bits [] is one of the 16 domains on the page controlled by this descriptor. Bits [] is not used now. It should be zero bits [31: 10] The base address of the page table is a pointer to the second-level refined page table, which provides the base address for accessing the second-level table. The second-level fine page table must be aligned at the 4 kb boundary. If the second-level detailed page table descriptor is read from the first-level table, the second-level descriptor is read as shown in Figure 3-5.  
3.7 second-level DescriptorHow does a rough second-level table map a virtual address range city in 4 kb, each refined second-level table reflects how the ing of the virtual address range city in 1kb. Those entries are page descriptors that can describe pages larger than 4 kb or 1 kb respectively. In this case, the descriptor must be repeated enough times to ensure that the page always uses the same descriptor, regardless of the virtual address on the page. There are four possibilities for a second-level descriptor, which are selected by the descriptor's bits [1:0. See table 3-2: · if bits [1:0] = 0b00, the associated virtual addresses are not mapped. Any access to these virtual addresses will result in a conversion error (fault ). Software can use the bits [31: 2] of such descriptors for their own purposes because they are ignored by hardware. We recommend that you maintain the correct access permission for the descriptor. · If bits [1:0] = 0b01, this entry is a large page descriptor describing a 64kb virtual address. See the conversion page reference. A large page descriptor must be repeated 64 times in a detailed second-level table, and 16 times in a rough second-level table to ensure that all virtual addresses are described. · If bits [1:0] = 0b10, this entry is a small page descriptor describing a 4 kb virtual address. See the conversion page for reference. A small page descriptor must be repeated four times in a detailed second-level table to ensure that all virtual addresses are described. There is only one instance in the rough second-level table. · If bits [1:0] = 0b11, this entry is the micropage descriptor, which describes the virtual address of 1 kb. See the conversion micro-page reference. In a detailed second-level table, you only need an instance of the micropage descriptor. The micropage descriptor cannot appear in the rough second-level table. If so, the result is unpredictable.  
Large page descriptor FieldThe fields of the large page descriptor have the following meanings: bits [1:0] indicates the type of the descriptor bits [] access limit of the fast promotion and buffer bits. These are used to control page access. The explanations for these bits are shown in Table 3-3. A large page is divided into four subpages. The access permission of ap0 encoding to the first child page. The access permission of AP1 to the second subpage. The access permission of AP2 to the third child page. The access permission of ap3 to the fourth subpage. Bits [] is not used now. It should be zero. Bits [31: 16] is used to form the corresponding location of the physical address. Small page descriptor FieldThe field of the small page descriptor has the following meanings: bits [1:0] indicates the type of the descriptor bits [] access limit of the fast promotion and buffer bits. These are used to control page access. The explanations for these bits are shown in Table 3-3. A small page is divided into four subpages. The access permission of ap0 encoding to the first child page. The access permission of AP1 to the second subpage. The access permission of AP2 to the third child page. The access permission of ap3 to the fourth subpage. Bits [31: 12] is used to form the corresponding location of the physical address. Micro-page descriptor FieldThe field of the micro-page descriptor has the following meanings: bits [1:0] indicates the type of the descriptor bits [] access limit of the fast promotion and buffer bits. These are used to control page access. The explanations of these bits are shown in Table 3-3. Bits [] is not used now. It should be zero. Bits [31: 10] is used to form the corresponding location of the physical address. 3.8 conversion large page referenceFigure 3-6 shows the complete order of converting a 64 kB large page in a rough second-level table. The conversion order page in the refined second-level table is similar, but the address of the second-level descriptor is determined by the detailed page table descriptor section. Note: ----------------------------- the 4-bit high in the page index overlaps the 4-bit low in the second-level table. In the rough page table, each page table entry must be repeated 16 times. In a large page table, each page table entry must be repeated 64 times.
----------------------------------- 3.9 conversion small page referenceFigure 3-7 shows the complete order of converting a small page of 4 kb in a rough second-level table. The conversion order page in the refined second-level table is similar, but the address of the second-level descriptor is determined by the detailed page table descriptor section. Note: ----------------------------- when a small page appears in a refined second-level table, the high 2 bits of the page index overlap with the low-level 2 bits of the second-level table, in a small page table, each page table entry must be repeated four times. -----------------------------------  
3.10 convert micro-page IndexesFigure 3-8 shows the complete process of converting a 1kb micropage in a detailed second-level table. Note: --------------------------- the micropage cannot appear in the rough second-level table. ---------------------------------

A 4-domain is a collection of sections, large pages, and small pages. The arm structure supports 16 fields. Domain access is controlled by two fields in the domain access control register. Because each field can quickly access the corresponding domain, the entire memory range can be quickly exchanged into and out of the virtual memory. Two domain access methods are supported: the user of the customer domain (Execution program, access data), and the access permission is supervised by forming a section or page of the domain. The Administrator controls the behavior of the domain (the current section and page in the domain, access to the domain) and does not form the section or page of the domain to supervise access permissions. A program can be a customer of some domains and also a manager of some other domains without access permissions to other domains. This allows flexible memory protection for applications to access different storage resources. Table 3-4 describes the bit encoding method of the domain access control register. 5 CP15 registersMMU is controlled by some bits of system control registers 2, 3, 4, 5, 6, 8, 10, and 1. 5.1 operations on coprocessor registersThe data transfer commands from the arm register to the coprocessor are MCR and mrcu mcrmcr, respectively. The data in the registers of the ARM processor is transferred to the coprocessor register. If the coprocessor fails to perform this operation, an undefined command exception is interrupted. Command syntax: MCR {cond} coproc, opcode1, RD, CRN, CRM {, opcode2} The Name Of The coprocesser for coproc command operation, standard name: PN, n is 0 ~ 15, here the source ARM Processor register CRN for the P15 opcode1 coprocessor specific opcode RD stores the first operand coprocessor register CRM stores the second operand coprocessor register opcode2 optional coprocessor operation code command example: the MCR P6, 2, R7, C1, c2mcr P7, 0, R1, C3, C2, 1u mrcmrc command transfers data from the coprocessor register to the ARM Processor register. If the coprocessor fails to perform this operation, an undefined command exception is interrupted. Command syntax: MRC {cond} coproc, opcode1, RD, CRN, CRM {, opcode2} The Name Of The coprocesser for coproc command operation, standard name: PN, n is 0 ~ 15, here the target ARM Processor register CRN for P15 opcode1 coprocessor specific opcode RD stores the coprocessor register for the first operand CRM stores the coprocessor register for the second operand opcode2 optional coprocessor opcode command example: MRC P6, 2, R7, C1, c2mcr P7, 0, R1, C3, C2, 1 MMU control bit of register 1 5.2The following bits of register 1 are used to control MMU: m (bit [0]) enables mmu0 = disables mmu1 = allows MMU on systems without MMU and protection units, this bit should be read as 0 and ignored. A (bit [1]) enables alignment error check 0 = Disable 1 = allow S (bit [8]) This is the system protection bit, see section 3-4. R (bit [9]) is the ROM protection bit. For details, see section 3-4. 5.3 register 2: base address of the conversion table 
When reading CP15 register 2, the physical address of the first-level conversion table of the current activity is returned in BITs [31: 14]. Bits [] is uncertain. When reading CP15 register 2, CRM and operand 2 are ignored and should be 0. When writing CP15 register 2, update the physical address of the first-level conversion table of the current activity in BITs [31: 14]. Bits [] should write 0 or the value previously read back. When writing CP15 register 2, CRM and operand 2 are ignored and should be 0. 5.4 register 3: domain access control 
When reading CP15 register 3, the value of the domain access control register is returned. The CRM and operand 2 are ignored and should be 0. Update the value of the domain access control register when writing CP15 register 3. The CRM and operand 2 are ignored and should be 0. The domain access control register contains 16 2-bit fields, which define the access permissions of the corresponding domain. See section 3-5. 5.5 register 4: ReservedRead and Write the CP15 register 4 unexpected results. 5.6 register 5: Error status FSRWhen reading CP15 register 5, the value of the FSR register is returned. FSR contains the last data error. Only the Lower 9 digits are valid, and the higher 23 digits are uncertain. FSR indicates the domain and type of access attempt when an exception occurs. Bit [8] returns 0bit [] indicating the type of access attempt by the domain bit [] When the dislocation occurs. the encoding of these bits is shown in Table 3-5 FSR updated when the data error occurs. The specific implementation determines whether to update the FSR when a command exception occurs. See section 3.6.2 "error Address Register (FAR) and error Status Register (FSR )". The CRM and operand 2 are ignored and should be 0. Writing FSR sets FSR as the written value. This is very useful for the program debugger and can be used to restore the value of FSR. The 24-bit high value should be 0 or the value read last time. The CRM and operand 2 are ignored and should be 0. 5.7 register 6: Error address far 
Read CP15 register 6 and return the far value. Far stores the virtual address accessed when an error occurs. Update far when data is incorrect. The specific implementation determines whether to update the FSR when a command exception occurs. See section 3.6.2 "error Address Register (FAR) and error Status Register (FSR )". The CRM and operand 2 are ignored and should be 0. Writing FSR sets far as the written value. This is very useful for the program debugger and can be used to restore the value of far. The 24-bit high value should be 0 or the value read last time. The CRM and operand 2 are ignored and should be 0. --- Note ------ if fcse is used, the modified virtual address is written to far when the memory fails to update far. · When the MRC command is used to read the far or MCR command is used to write the far, its value is treated as data, so the address generated by fcse is not modified. ------------ 5.8 register 8: TLB FunctionWhen CP15 registers 8 is used to control TLB, It is a read-only register. Table 3-6 shows the defined TLB function and the CRM and the second <opcode2> value in the MCR command. Using a combination of CRM and opcode2 that is not in the table will lead to unpredictable results. If any of the following operations is used in the implementation of a single TLB, the same function will be implemented in a single TLB: · invalid command TLB (invalidate instruction TLB) · invalidate instruction single entry) · invalid entire data TLB (invalidate entire data TLB) · invalidate data single entry otherwise, if you execute a function that is not related to a specific implementation, it will lead to uncertain results. The result of trying to read CP15 register 8 using the MRC command is unknown. When only a small amount of memory is remapped, invalid single-entry operations can be used to improve performance in some implementations. For each remapped memory area (segment, small page, or large page), an invalid single entry needs to be executed on the virtual address of the memory area. Performance improvement comes from the absence of reloading TLB entries related to the memory areas not remapped. --- Note ------ the performance improvement of invalid single-entry operations is not guaranteed. The specific implementation can be that a single request entry is invalid until the entire TLB is invalid. -------------- Be careful ------ When the memory is remapped, The TLB entry related to the old ing must be invalidated. Otherwise, two TLB entries may overwrite the virtual address range. In the best case, accessing such a coverage of the virtual address range may have unpredictable results; in some implementations, MMU may even be physically damaged. It is strongly recommended that you be careful when re- ing the memory to make The TLB ineffective as appropriate.

------------
--- Note ------ if fcse is used, some functions in Table 3-6 are passed to the virtual address of CP15 as data. This means that no address changes are generated by fcse for them. ------------ 5.9 register 10: TLB lockedIt takes some time to execute the traversal of the conversion table, especially when accessing the slow primary storage. In The Real-Time Interrupt Processing Program, when TLB does not contain the conversion and/or data to be accessed, the Interrupt Delay is extended. TLB locking is a feature of some arm storage systems that allow loading the traversal results of specific conversion tables into TLB. This method will not be overwritten by the result of later conversion table traversal. Set by CP15 register 10. Set W = log2 (number of TLB entries). If you need to use round-up, the format of CP15 register 10 is: if the specific implementation includes separate commands and data TLB, there are two different registers, which are selected by the opcode2 field in the MCR or MRC command accessing register 10: opcode2 = 0 select data TLB lock register opcode2 = 1 SELECT command TLB lock register if the specific implementation only has a unique TLB, then only one register, opcode2 field should be 0. The total CRM value in the MCR or MRC command of access register 10 should be 0. Write register 10 has the following results: the victim field indicates which TLB entry is replaced by the conversion table traversal result when TLB fails (MISs) the next time. The base field contains the TLB replacement policy. Only the TLB entry from (base) to (TLB entry-1) is used. victim should be in this interval. When the result of traversing the conversion table is written to the TLB entry, if p = 1, it is protected and cannot be affected by the entire TLB failure operation in register 8; if P = 0, the Operation will fail. --- Note ------ if the TLB entry is not the nth power of 2, the base or victim value written to the TLB entry greater than or equal to the number of TLB entries will be uncertain. ----------- Read register 10 returns its value. TLB lock ProcessGenerally, the process of locking n TLB entries is as follows: 1. disallow interruptions to ensure that exceptions are not generated when this process is executed. if a command TLB or unique TLB is locked, use base = N, Index = N and P = 0 to write it to the appropriate version of register 10. If possible, disable the branch prediction function, which is hard to comprehend by prefetch other commands. 3. invalidate the entire TLB to be locked. 4. If the command TLB is locked, make sure that the TLB entry related to the command to be prefetch in the remaining locking process is loaded. (Note where the lock starts. Generally, a TLB entry may contain all of these. In this case, the first command after The TLB is invalidated can complete this function. If the data TLB is locked, make sure that the TLB entry related to the data to be accessed during the rest of the lock process is loaded. This includes the embedded text (Inline literals) used by the Code (it is usually better to avoid using embedded text during the locking process, and put all the data in the area included by a TLB entry, then load a data from there) If a unique TLB
Locked to execute all the above processes. 5. I loops from 0 to N-1 A. writes to register 10 with base = I, Index = I and P = 1. B. forced conversion table traversal to the memory area of the conversion table traversal result locked at TLB entry I: * If the data TLB or the unique TLB is locked, load a data from that region * if the directive TLB is locked, use the directive prefetch High Speed Buffer register 7 described on the B5-15 page to generate directive prefetch in that region. 6. Use base = N, Index = N and P = 0 to write to register 10. --- Note ------ if fcse is used, pay attention to step 5B, because: · if data TLB is locked or the unique TLB is locked, the address for loading data commands will be modified by fcse. · If the command TLB is locked, the address used in register 7 will be treated as data and will not be modified by fcse. To reduce obfuscation, the recommended locking process should be: · starting from fcse prohibition (set PID to 0) · use an appropriate PID value or a high 7-bit virtual address to generate a modified virtual address. ----------- TLB unlock ProcessUse the above process to unlock the locked TLB part: 1. use register 8 to invalidate each locked single entry. use base = 0, Index = 0, and P = 0 to write to register 10. --- Note ------ the first step is to ensure that the entry of P = 1 is not left in TLB. If they are left in TLB, the entire TLB will not be invalidated in the subsequent TLB locking process (Step 3.

MMU Management Mechanism