MMU-related instruction learning (1) (mainly page table setting instructions)

Author: wogoyixikexie @ gliet

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Next, let's take a look at this figure and look at it with instructions. However, I always think this figure is very different from the settings described in the program.

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Here we will add the role of MMU and the consequences of not using MMU.

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MMU converts virtual addresses into physical addresses, controls memory access permissions, and determines the write buffer and cache of memory pages. If MMU is disabled, the virtual addresses correspond to physical addresses (equal)

 

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Structure of the page table

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Arm MMU has a multi-page table structure, which can be divided into two levels: L1 and L2. L1 becomes the homepage table, which can contain two types of table items: it can point to the starting address of the L2 page table and the page table items converted into 1 MB pages. L1 homepage table can also be called a segment page table.

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L1 page table item settings

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A section page table entry points toa1mb section of memory. The upper 12 bits
The page table entry Replace the upper 12 bits of the virtual address to generate the physical
Address. A section entry also contains the domain, cached, buffered, and access permission
Attributes, which we discuss in section 14.6.
A coarse page entry contains a pointer to the base address of a second-level coarse page
Table. The coarse page table entry also contains domain information for the 1 MB Section
Of virtual memory represented by the L1 table entry. For Coarse pages, the tables must be
Aligned on an address multiple of 1 kb.
A sort ne page table entry contains a pointer to the base address of a second-level sort ne page
Table. The specified ne page table entry also contains domain information for the 1 MB section
Virtual Memory represented by the L1 table entry. Fine page tables must be aligned on
Address multiple of 4 kb.
A fault page table entry generates a memory page fault. The fault condition results in
Either a prefetch or data abort, depending on the type of Memory Access attempted.
The location of the L1 master page table in memory is set by writing to the CP15: C2
Register.

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Base Address of L1 conversion table

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The CP15: C2 register holds the translation table base address (TTB)-an address pointing to the location of the master L1 table in virtual memory (indicating the address of the L1 page table in the virtual memory ). figure 14.7 shows the format of CP15: C2 register.

 

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L2 page table item

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Types of L2 page table items

 

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The specific settings are as follows.

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We can see from the above that these things are all the same. Continue to look at them and we can find the answer today.

 

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Page table search

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1. Single-step search (in fact, only the first-level page table is used: in the case of streaking)

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2. Two-Step search (actually using the Level 2 page table: used when using the Linux/wince operating system)

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As shown above, when two-level page tables are used, the first-level page table stores the directory of the second-level page table, and the second-level page table stores the conversion table.

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For more detailed analysis, see MMU instruction learning (2) (mainly page table setting instruction. Or the forum post I posted.

Http://topic.csdn.net/u/20081231/10/bbde79c2-2884-48e3-9718-90d7fcc1afa8.html? Seed = 1947589160

Reprinted please indicate: The author wogoyixikexie @ gliet. Guilin University of Electronic Science and Technology Department 1 Association of Science and Technology, original address: Workshop.