Motivation for learning timequest (I)

The materials of heijin power are still very valuable. Through modeling, I can always implement a given time series relationship. However, this is always a basic capability. It only serves the subsequent modeling services. Therefore, at this stage, my capabilities are still very limited. I believe that I will surely become a cool man and be able to stand alone. Borrow a sentence from a classmate: look up at the stars and be down-to-earth. Now let's learn the timing constraints of FPGA.

A Time Series constraint requires a time series. In the previous modeling, we used to imagine whether the timing sequence was satisfied or not, but there were also actual constraints. However, the timing constraints here are constraints made to familiarize themselves with TQ. That is, there is no specific timing requirement. It was not until recently encountered that the highest operating frequency of the module was. For example, in 64-bit processors, four-level pipelines increase the computing speed. I have never known how it gets the highest running frequency. Until yesterday, by chance, it was estimated that TQ analysis was a good method (there should be other time series analysis tools ). That is, there are time series requirements. For example, a 64-bit full-processors can run at a maximum frequency of 100 MHz. So how can we analyze whether modeling meets the highest frequency? This can be obtained through TQ. This is why I want to use the TQ constraint.

Figure 1: Relationship between ideal time series

 

 

Ideal persistence relationship diagram:

 

 

 

Hardware physical build margin:

 

 

Setup relationship is a process of evaluating (calculating) setup lack.

You can create a margin: Data lock time (datarequiretime)-data arrival time (dataarrivetime) = (10 + 2-1.4)-(tclk1 + TCO + tdata) = 10.6-4 = 6.6ns.

 

 

 

What is the relationship between establishing a positive margin and establishing a link between reg1 and reg2 that is unqualified? As long as the margin is greater than 0, there is no problem in establishing the relationship between the two registers.

The lock time is basically the "ideal Relational Value". For the ideal Relational Value, see the previous section. The ideal established relationship value is equivalent to the lock time in evaluating the data lock time.

 

Hardware physical remaining balance:

In the concept of a register, "retention time" indicates that after a register reads data, it takes a minimum period of time to "ensure the stability of the Data lock.

However, the definition of "remaining margin" refers to: between two nodes (registers, in the process of analyzing and maintaining the relationship, "How much time can be left to the Register to ensure the stability of the stored data ".

Data hold time = Start Time + tclk1 + TCO + tdata + data cycle time. (Time when the data output in register 1 remains unchanged)

Data required time = Lock edge + tclk2 + Th.

Retention margin = Data Retention Time-data lock (GET | read) time.

 

Remaining allowance = (data retention time) (10 + 3.2 + 0.8)-(Data lock storage (GET | read) time) (10 + 2 + 1.4) = 0.6

 

 

Here I want to say one more thing: When Triggering along modeling, I always worry about whether the high level of a pulse can be detected in the condition judgment. I didn't understand timing analysis enough. Now my answer is timing analysis. If the relationship is established and maintained, it can be detected in the condition judgment.

 

 

 

Whether it is an ideal established Relational Value or an ideal maintained Relational Value, "they serve as a reference and simplify the timequest model.

Because the process of finding the "keep margin" is too cumbersome, in order to simplify the process of finding the keep margin, keep the margin and create a share of the same formula, therefore, this "ideal persistence relationship value" is required.

Data arrival time = start edge + tclk1 + TCO + tdata (Note: Data hold time is not the data hold time, so it is not added to the data cycle time)

Data lock (GET | read) time data required time = Lock edge + tclk2 + Th = ideal persistence Relationship Value + tclk2 + Th
(Note: the formula used to evaluate the latencies of the lock edge is similar to the formula used to obtain the data lock time when the margin is established)

 

Data arrival time = start edge + tclk1 + TCO + tdata = 0 + 3.2 + 0.2 + 0.6 = 4ns
Data required time = Lock edge + tclk2 + Th = ideal persistence Relationship Value + tclk2 + Th = 0ns + 2ns + 1.4ns = 3.4ns

Remaining allowance = data arrival time-data lock (GET | read) time = 4ns-3.4ns = 0.6ns

My understanding: obviously this is correct. Because the latch edge of reg2 is the lunch edge of reg1, that is, their time points are overlapped (of course, this is in the ideal time series ). In the time series of physical hardware, although there is latency, their ideal persistence relationship remains unchanged. Or: regardless of how the latency of clk1 and clk2 changes, their cycle is 10ns. For example

 

Figure 1.6.9 shows how to use your ass to maintain the margin. In other words, "Use the red part of the next Startup edge to remove the green part of the current lock", and use the "ideal persistence Relationship Value ".

 

 

 

 

 

 

The formula for calculating the margin is:
Remaining allowance = data lock time-data arrival time setup slack = data required time-data arrival time
Data arrival time = start edge + tclk1 + TCO + tdata
Data Retrieval time data required time = Lock edge + tclk2-Tsu = ideal Relational Value + tclk2-Tsu

The formula for calculating the margin is: (if you use your ass)
Remaining allowance = data arrival time-data acquisition time hold slack = data arrival time-data required time
Data arrival time = start edge + tclk1 + TCO + tdata
Data Retrieval time data required time = Lock edge + tclk2 + Th = ideal persistence Relationship Value + tclk2 + Th

 

In addition, I will explain the formulas used in the timequest model and what appears in the physical sequence. If you follow the common method to learn timequest, it is easy to hit the wall, or it will be trained as a pure formula user. The timequest model is a very interesting thing. If you use a pure formula method, you will not be able to experience the fun of timequest, or enjoy the fun of learning.

 

 

Motivation for learning timequest (I)