MSP430 G2553 Comparator comparator_a+, data flowchart DFD, state transition Graph STD

First, ca+ structure

The msp430g2553 is provided with a comparator comparator_a+ (ca+), as shown in the construction block diagram.

Second, input & output

As shown, the comparator has a co-axial input (v+) and a reverse input (V-). With the software setup, the v+ end can be connected to one of the CA0~CA2 three external pins, or one of the three internal voltage references; The V-end can be connected to one of the Ca1~ca7 seven external pins, or one of three internal voltage references. The internal voltage reference can be 0.5*VCC, 0.25*VCC, or the on-off voltage of one of the internal diodes (about 0.55V).

The output signal can be connected to the timer's external clock input, or caout the corresponding pin, and when the output signal changes, the CAIFG interrupt can be triggered.

CAx, caout corresponds to the msp430g2553 pin as shown.

Third, the relevant settings register

The main registers of ca+ are CACTL1, CACTL2, CAPD three. Wherein the CAPD is used to disconnect the digital circuit portion connected to the GPIO pin to improve the performance of the ca+, in fact, when a pin is set to ca+ input, CAPD automatically sets the position, so for CAPD operation generally do not need to care (unless the pin is also used to enter a digital signal).

-P2cax bit segment of the CACTL2 register: Select the pin corresponding to the input signal.

-Caex bit of the CACTL1 register: Toggles the v+, V-input signal. This feature is commonly used when the input signal is very close.

-Caon bit of the CACTL1 register: ca+ is turned off/on.

-The Carefx and Carsel bits of the CACTL1 register: The CAREFX bit segment is used to select the ca+ reference voltage and can be used for 0.5*VCC, 0.25*VCC, or ~0.55v;carsel bits to select a reference voltage to connect to the v+ or V-end. Note that the internal reference voltage must be closed when the v+ and V are connected to the external pins.

-CACTL2 Register's CAF bit: off/on input signal filtering. recommended to open.

-Cashshort bit of the CACTL2 register: The input signal is short-connected. Generally not used.

Interesting examples of 四、一个

The potentiometer is connected to the P1.1, and when the P1.1 voltage is higher than 0.5*VCC, the LED flashes; otherwise the LED lights go off.

1#include"io430.h"2 3 #defineLED1 BIT0//Red4 5 #defineTRUE 16 #defineFALSE 07 8 #defineLow_input 09 #defineHigh_input 1Ten  One //global variable A CharState =Low_input; - CharFlash = FALSE;//start with low input, no flash on LED -  the voidMainvoid) - { -     //Stop watchdog timer to prevent time out reset -Wdtctl = Wdtpw +Wdthold; +      -     //LED Setup +P1out =0; AP1dir |=LED1; at      -     //DCO Setup -BCSCTL1 = Calbc1_1mhz;//running at 1MHz -Dcoctl =Caldco_1mhz; -      -     //ACLK Setup inBCSCTL3 |= lfxt1s_2;//aclk Source:vlo, measured as 10kHz -BCSCTL1 |= Diva_3;//ACLK = VLO divided by 8:1.25khz to      +     //timer0_a Setup -TA0CCR0 = --1;//Timer Overflow freq:1250/250 = 5Hz (0.2s) theTa0cctl0 = CCIE;//Enable interrupt *Ta0ctl = tassel_1 + mc_1 + taclr;//aclk, no Div, up mode, clear timer $     Panax Notoginseng     //comparator_a+ Setup -CACTL1 = caref_2 + Carsel + caie;//0.5 Vcc ref on V, enable interrupt on rising theCACTL2 = p2ca4 + CAF;//input CA1 (P1.1) on v+, filter on +CACTL1 |= Caon;//Turn on Comparator A      the __enable_interrupt (); + LPM3; -      $ } $  - #pragmaVector = Timer0_a0_vector -__interruptvoidCCR0_ISR (void) the { -     //TA0CCR0 flag Clearing is automaticWuyi     if(Flash = =FALSE) the     { -P1out &= ~led1;//led off Wu     } -     Else About     { $P1out ^= LED1;//Toggle LED -     } - } -  A #pragmaVector = Comparatora_vector +__interruptvoidCOMPA_ISR (void) the { -     Switch(state) $     { the      CaseLow_input: the         if((CACTL2 & caout) = =0x01) the         { theState =High_input; -CACTL1 |= caies;//value High, so watch for falling edge inFlash = TRUE;//Let LED Flash the         } the          Break; About      CaseHigh_input: the         if((CACTL2 & caout) = =0x00) the         { theState =Low_input; +CACTL1 &= ~caies;//value Low, so watch for rising edge -Flash = FALSE;//Turn LED off the         }Bayi          Break;  the     } the}

The interesting part of this example is the presentation of two important concepts: the data Flow Diagram, the DFD, and the state Transition Diagram, STD. Two interrupt programs handle interrupts from Timer0_a and ca+ respectively, forming two "process", which have their own unique variables/parameters, while also sharing the flash (led flashing) this variable. In addition, the ca+ interrupt program contains the High_input and low_input two states and is a very simple state machine.

The program's DFD and ca+ interrupt program's STD as shown.

MSP430 G2553 Comparator comparator_a+, data flowchart DFD, state transition Graph STD