MSR and Mrs commands

 

(To) http://blog.ednchina.com/yannzi/197679/message.aspx

Http://blog.sina.com.cn/s/blog_4117d8560100b432.html

1. Status Registers are transferred to general register commands.
Function: transfers the Status Register content to a common register.

Format:
Mrs {<condition code >}rd, CPSR} spsr
Where:
Rd target register. RD does not allow R15.
R = 0 transfers the content in CPSR to the destination register.
R = 1 transfer the content in spsr to the destination register.

Note:
Mrs and MSR are used in combination as part of the read-Modify-write sequence for updating dsrs. For example, change the processor or clear the flag Q. Note: When the processor is in user or system mode, you cannot try to access the spsr.
This command does not affect the condition code mark.
Example:
Mrs r0, crsr; transmits content in CPSR to R0
Mrs R3, spsr; transmits the content in spsr to r3

2 General registers send commands to status registers
Function: transfers the content of the General Register to the Status Register.

Format:
MSR {<condition code> cpsr_f | spsr_f, <# ommed_8r>
MSR {<condition code> CPSR _ <field> | spsr _ <field>, RM
Where:
<Field> fields can be one or more of the following: (from right to left)
C: control domain shielding fields (0th-7th bits in the "SRS" field );
X: extended domain shielding field (8th-15th bits in the "SRS" field );
S: The Status domain shielding field (16th-32nd bits in the SRS );
F: indicates the domain blocking field (24th-31st bits in the SRs ).
The expression of the immed_8r value numeric constant. The constant must correspond to an 8-Bit Bitmap. This bitmap shifts an even number cyclically in 32-bit characters.
Rm source register.

Note:
The same as the previous command (MRS ).
Example 1: set N, Z, C, and V.
MSR cpsr_f, # & f0000000; valid only for high positions. Other values must be 0.
Example 2:
Only set the C flag, and retain the N, Z, and V signs.
Mrs r0, CPSR; transmits content in CPSR to R0
ORR r0, R0, # & 1f; Set 29th bits of R0
MSR cpsr_c, R0; then transmits the content in R0 to CPSR

 

Example: Set the CPU to work in the super protection mode (svc32)

@ Set the CPU to svc32 Mode

Mrs r0, CPSR

 

@ Save the CPSR content to r0. use the Mrs command: special register to access through register.
@ CPSR the current program status register format is as follows:

@ 31 30 29 28 27 26 25 24 ~ ~ ~ 8 7 6 5 4 3 2 1 0
@_________________________________________________________
@ | N | z | c | v | * | *** | I | f | T | M4 | m3 | m2 | M1 | M0 |
@

Bic r0, R0, # 0x1f

@ Bic command (bit clear): R0: = R0 and (not OP2). The command above aims to set bit0 ~ Bit4 is cleared.

 

ORR r0, R0, #0xd3

@ R0: = R0 or 0xd3. after the preceding three commands are executed, the R0 value is ************************** 11*1 0011.

 

Msr cpsr, R0

@ Save R0 to CPSR. Note: MSR commands are dedicated General registers. The commands in special function registers correspond to Mrs commands.

 

Note: The preceding commands show that two functions are implemented. 1. Disable external interrupt (IRQ) and fast interrupt (FIR ). 2. Set the system to svc32 (Super protection), that is, M4 ~ M1 = 10011