The development environment is: uClinux-2.6, bf561, the compiler is vdsp4.5
1 norflash: am29lv320mtAm29lv320mt is a 4 m, 16-bit norflash that supports the CFI interface. Its address space is 0x2000 0000 ~ 0x2040 0000. 1. Configure asynchronous memory. The following are related macros: # define limit 1 # define limit 1 # define limit 1 # define config_c_b2pen 1 # define config_c_b3pen 1 # define limit 0x7bb0 # define limit 0xffc2 # define limit 0xffc2 # define limit 0xffc22, define command set: # define config_mtd_cfi_amdstd 1 3. define the basic flash parameters: # define config_ebiu_flash_base 0x20000000 # define config_bfin_flash_size 4 4. Add Drivers/MTD/ Maps/ezkit561.c. 5. Modify # define ezkit561_flash_base 0x20000000 # define ezkit561_flash_size 0x00400000 to the address and size of the on-board flash. 6. Modify the ezkit56w.parts partition to define the expected value. Done.
2 NAND: k9w8g08u1mK9w8g08u1m is a 1 gb nand Flash, which is made up of two 512m chips. Its Rb1 and Rb2 are connected to pf4 and pf5, CE1 and CE2 are connected to pf0 and pf1, ale is connected to pf2, and cle is connected to PF3. Drivers in uClinux are similar to those in U-boot but slightly different. 1. Add Drivers/MTD/NAND/bfin_nand.c. 2. Modify the address definition: # define bfin_nand_base 0x29000000/* config_bfin_nand_base */3. Modify the PF port setting code in the bfin_nand_init function: /* configure GPIO-BFIN_NAND_READY */* pfio0_dir | = 0x000f; // set pf0 ~ PF3 as output, others as inputs ASM ("ssync;"); * pfio0_inen | = 0x0030; // enable input buffer for pf4, pf5 ASM ("ssync ;"); 4. Modify the following three control functions: static void bfin_hwcontrol (struct mtd_info * MTD, int cmd, unsigned int CTRL) {register struct nand_chip * This = MTD-> priv; if (cmd = nand_1__none) return; If (CTRL & nand_cle) {* pfio0_flag_s = 0x04; * pfio0_flag_c = 0x08;} If (CTRL & nand_ale) {* pfio0_flag_c = 0x04; * Pfio0_flag_s = 0x08;} This-> io_addr_r = This-> io_addr_w;/* drain the writebuffer */ASM ("ssync ;"); // _ builtin_bfin_ssync (); writeb (CMD, p_nand); ASM ("ssync;"); * pfio0_flag_c = 0x04 | 0x08; /* If (cmd = nand_assist_none) return; If (CTRL & nand_cle) writeb (CMD, p_nand + bfin_nand_cle); else writeb (CMD, p_nand + bfin_nand_ale); ssync (); */} int bfin_device_ready (struct mtd_info * MTD) {return (* P Fio0_flag_d & 0x30) = 0x30 )? 1: 0; // return gpio_get_value (config_bfin_nand_ready);}/*** nand_select_chip-[Default] control ce line * @ MTD: MTD device structure * @ chip: chipnumber to select, -1 for deselect ** default select function for 1 chip devices. */static int current_chip =-1; static void bfin_select_chip (struct mtd_info * MTD, int chip) {struct nand_chip * This = MTD-> priv; current_chip = chip; Switch (CHIP) {ca Se-1: * pfio0_flag_s = 0x03; break; Case 0: * pfio0_flag_c = 0x01; ASM ("ssync;"); * pfio0_flag_s = 0x02; break; case 1: * pfio0_flag_c = 0x02; ASM ("ssync;"); * pfio0_flag_s = 0x01; break; default: Bug ();} ASM ("ssync; ");} 5. Modify the partition definition in partition_info. Done. Note that the corresponding partitions are added after the nandflash and norflash detection are completed. The mtdblock number used for system startup may change. By default, norflash adds three partitions and nandflash adds two partitions. Therefore, the root at startup is changed from/dev/mtdblock0 to/dev/mtdblock5.
