Multi-path selector, latches, and full processors are designed with VHDL.

1.2 select 1 multi-path Selector

 1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 ENTITY mux21 IS 4   PORT ( a,b : IN STD_LOGIC; 5            s : IN STD_LOGIC; 6            y : OUT STD_LOGIC ); 7 END ENTITY mux21; 8   9 ARCHITECTURE one OF mux21 IS10   BEGIN11      y <= a WHEN s = ‘0‘ ELSE12           b WHEN s = ‘1‘;13 END ARCHITECTURE one;

2. latches

 1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3  4 entity latch is 5     Port ( d : in STD_LOGIC; 6          ena : in STD_LOGIC; 7            q : out STD_LOGIC 8          ); 9 end entity latch;10 11 architecture one of latch is12  signal sig_save : STD_LOGIC;13  begin14    process (d,ena)15     begin16     17      if ena = ‘1‘ then18      sig_save <= d;19      end if ;20      21      q <= sig_save ;22    end process ;23 end architecture one;

3. Full Processors

1 -- or logical description 2 library IEEE; 3 Use IEEE. std_logic_1_4.all; 4 5 entity or2 is 6 port (A, B: In std_logic; C: Out std_logic); 7 End Entity or2; 8 architecture FU1 of or2 is 9 begin10 C <= A or B; 11 end architecture FU1; 12 13 -- semi-processors description 14 library IEEE; 15 use IEEE. std_logic_1_4.all; 16 17 entity h_adder is18 port (A, B: In std_logic; CO, so: Out std_logic); 19 End Entity h_adder; 20 architecture fh1 of h_adder is21 begin22 so <= (A or B) and (a nand B); -- Role of Non: implement 1 + 1 = 023 Co <= not (a nand B); -- non: 0 is returned only when 1 NAND 1 is implemented, and 124 end architecture fh1 is returned in other cases; 25 26 -- top-level design description for the full extender 27 28 library IEEE; 29 Use IEEE. std_logic_00004.all; 30 31 Entity f_adder is32 port (AIN, bin, CIN: In std_logic; 33 cout, sum: Out std_logic); 34 End Entity f_adder; 35 36 architecture fd1 of f_adder is37 component h_adder38 port (A, B: In std_logic; 39 Co, so: Out std_logic); 40 end component; 41 component or242 port (A, B: in std_logic; 43 C: Out std_logic); 44 end component; 45 signal D, E, F: std_logic; 46 begin47 U1: h_adder port map (A => Ain, B => bin, CO => D, so => E); 48 U2: h_adder port map (A => E, B => Cin, CO => F, so => sum); 49 U3: or2 port map (A => D, B => F, c => cout); 50 end architecture fd1;

 

Multi-path selector, latches, and full processors are designed with VHDL.