MX51 IPU csi0 CCIR code register Configuration

Turn: http://blog.csdn.net/kickxxx/article/details/6763644

Each ipu csi has three registers: csi0_ccir_code_1, csi0_ccir_code_2, csi0_ccir_code_3

Csi0_ccir_code_3 is relatively simple. It records the ff 00 in the ff 00 00 xy of the bt656 time series signal,

The XY mode is recorded in csi0_ccir_code_1 and csi0_ccir_code_2, where csi0_ccir_code_1 records field0; csi0_ccir_code_2 records filed1

The matching mode involves three flags: h v f:

H: H = 0 sav signal, H = 1 EAV Signal

V: V = 0 indicates active video, and V = 0 indicates no valid video data for this row.

F: F = 0 even, F = 1 odd

In fact, F doesn't matter, because it doesn't matter who is in the parity field (you can adjust it later), mainly configuring H and V; the best part of 51rm is that it does not explain the order of these symbols.

The sequence is h v f.

In addition, IPU seems to assume that the bt656 data will not go wrong and only synchronize the first frame. If the ad chip is unstable, the bt656 input will lose the data and the result will be Frame loss forever.