My FPGA Learning Journey (10)--Experimental digital tube driver

According to the Black Gold AX301 Manual, the digital tube position selected signal is named sel[5:0], wherein SEL[5] corresponds to the leftmost digital tube, and sel[0] corresponds to the right-most digital tube, as a convention, in the following description we call the digital tube 5 and digital tube 0. The De Shun signal of the digital tube is named Dig[7:0];dig[7] is the decimal point dp,dig[6] is the digital tube g segment, Dig[0] is a segment, other analogy can be.

Because the digital tube De Shun signal is common, theoretically it is impossible to display six different characters at the same time, but because of the visual residue of the human eye, as long as we show each number in turn, we can deceive the eyes to show the purpose of multiple digits, assuming that the number to display is 123456, and the other binary BCD code is The ' B 0001_0010_0011_0100_0101_0110 can be abbreviated to ' h123456 ' to achieve the following process:

2. First enable digital tube 0, turn off other digital tubes: SEL = 6 ' b111_110, the displayed value is 6,dig = {1,dig[6:0]} = 7 ' b1_000_0010;
4. The second step enables the digital tube 1, close other: SEL = 6 ' b111_101, the displayed value is 5,dig = 7 ' b1001_0010;
6. Similarly SEL = 6 ' b111_011, showing 4 DIG = 7 ' b1001_1001;
8. Similarly SEL = 6 ' b110_111, showing 3 DIG = 7 ' b1011_0000;
10. Similarly SEL = 6 ' b101_111, showing 2 DIG = 7 ' b1010_0100;
12. Similarly SEL = 6 ' b011_111, showing 1 DIG = 7 ' b1111_1001;
14. Back to step one.

SEL values can be moved to the left to practice, because the transistor has a frequency limit, scanning frequency should not be too fast, the required frequency can be achieved by the above-mentioned divider, the divider code is as follows:

In the counter[16] can be modified, I tried 17, 18, 19 is too slow, digital tube flash of the powerful calculation of the frequency of the division:

F =50mhz/(2^ (16+1)) = 50_000_000 hz/(2^17) = 381.469726 Hz ~ ~ 381.47 Hz

For the control module, this module functions more complex:

1. First, a 0 to 5 continuous cycle of the low-speed counter dig_num as a reference value.
2. When Dig_num is 0 o'clock, the digital tube 0 is lit and the value of low three bits [3:0] in Num is separated (6 in this case) to display.
3. When Dig_num is 1 o'clock, light the digital tube 1, separate num[7:4] to display (this separates 5).
4. When dig_num = 2 ~ 5 o'clock, the situation is similar.
5. Any time the value in display is converted to the De Shun signal required by the digital tube.

Syntax used in this example: Decimal ' d, Hex ' H, octal ' O, binary ' B must be careful, very easy to mistake

Finally, the top-level module, which specifies the characters to display:

If you feel it is difficult to display six characters at the same time, you can choose to light two first, then increase in order. Well, this is the end of the story.

My FPGA Learning Journey (10)--Experimental digital tube driver