Nand ECC Calibration and error correction

Original source: http://linux.chinaunix.net/techdoc/net/2009/07/15/1124340.shtml

The full name of ECC is error Checking and Correction, which is an error detection and correction algorithm for NAND. If the operation timing and circuit stability is not a problem, NAND Flash error generally does not cause the entire block or page can not read or all errors, but the entire page (such as 512Bytes) only one or a few bit error. ECC can correct 1 bit errors and detect 2 bit errors, and the calculation is fast, but more than 1 bits of error can not be corrected, more than 2 bits of error is not guaranteed to detect.
Verification Code Generation algorithm: ECC checksum operates on 256 bytes of data each time, including column checksum and row checksum. For each bit bit to be verified or, if the result is 0, it is indicated to contain an even number 1, if the result is 1, it indicates that there is an odd number of 1. The column validation rules are shown in table 1. The 256-byte data forms a 256-row, 8-column matrix with each element representing a bit bit.

Chart 1 line address check generation rule

where CP0 ~ CP5 is a six bit bit, which represents column Parity (columns polarity),
CP0 is the polarity of the No. 0, 2, 4, and 6 columns, CP1 is the polarity of the 1th, 3, 5, 7 columns,
CP2 is the polarity of the No. 0, 1, 4, and 5 columns, CP3 is the polarity of the 2nd, 3, 6, 7 columns,
CP4 is the polarity of the No. 0, 1, 2, and 3 columns, and CP5 is the polarity of the 4th, 5, 6, 7 columns.
Represented by the formula is: CP0=BIT0^BIT2^BIT4^BIT6, the No. 0 column internal 256 bit XOR or followed by the 2nd column 256 bit XOR, and then the 4th column, 6th column each bit XOR, so that CP0 is actually 256*4= 1024 bit XOR result. CP1 ~ CP5 and so on.
The row check is shown in Figure 2 below:

Chart 2 line check code generation rule

where RP0 ~ RP15 is a 16 bit bit, indicating row Parity (line polarity),
RP0 for No. 0, 2, 4, 6 、.... 252, 254-byte polarity
RP1-----1, 3, 5, 7 ... 253, 255
RP2----0, 1, 4, 5, 8, 9.....252, 253 (handling 2 bytes, skipping 2 bytes)
RP3----2, 3, 6, 7, 10, 11.....254, 255 (skipping 2 bytes, processing 2 bytes)
RP4----Processing 4 byte, skipping 4 bytes;
RP5----Skips 4 byte, processing 4 bytes;
RP6----Processing 8 bytes, skipping 8 byte
RP7----Skips 8 byte, processing 8 bytes;
RP8----Processing 16 bytes, skipping 16 byte
RP9----Skips 16 byte, processing 16 bytes;
RP10----Processing 32 bytes, skipping 32 byte
RP11----Skips 32 byte, processing 32 bytes;
RP12----Processing 64 bytes, skipping 64 byte
RP13----Skips 64 byte, processing 64 bytes;
RP14----Processing 128 bytes, skipping 128 byte
RP15----Skips 128 byte, processing 128 bytes;
As can be seen, RP0 ~ RP15 each bit bit is 128 bytes (that is, 128 rows) that is the result of 128*8=1024 bit bit XOR.
In summary, the 256-byte data coexist into 6 bit column check results, 16 bit of row check results, a total of 22 bit. Use 3 bytes in the NAND to hold the check result, the extra two bit position 1. The order of storage is shown in Figure 3 below:

Figure 3 ECC Check Code organization structure

In k9f1208, for example, each page page contains a 512-byte data area and a 16-byte OOB area. The first 256 bytes of data generated 3-byte ECC checksum, the last 256 bytes of data generated 3-byte ECC checksum, a total of 6-byte ECC checksum code is stored in the OOB area, the location is the OOB area of the No. 0, 1, 2 and 3, 6, 7 bytes.

Algorithm of generating ECC checksum code table source code:

#include "StdAfx.h"/*  * =================================================================================== = =  *  *       filename:  nand_ecc.c  *  *    Description:    *  *        version:  1.0  *         created:  June 04, 2009 15:10 20 sec  *       revision:  none  *       compiler:  gcc  *  *          author:  Li Hongwang (MN), hoakee@gmail.com  *         company:  University of Science and Technology of the China  *  * =================== ==================================================================  */#include <stdio.h> #define           BIT0 (x) &NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&Nbsp;   (((x) &0x01) >>0) #define          BIT1 (x)           (((x) &0x02) >>1) #define           BIT2 (x)          ((((x) &0x04) >>2) #define           BIT3 (x)          (((x) & 0x08) >>3) #define          BIT4 (x)           (((x) &0x10) >>4) #define          BIT5 (x)          (((x) &0x20) >>5) #define           BIT6 (x)          ((((x) &0x40) >>6) #define          BIT7 (x)          (((x) &AMP;0X80) &GT;&GT;7) typedef unsigned char byte;

BYTE nand_ecc_precalc_table[256];

void Makeecctable () {    byte i=0;     byte XData;     for (i=0; i<255; i++)     {        xData = 0; & nbsp;       if (BIT0 (i) ^bit2 (i) ^BIT4 (i) ^bit6 (i))   //cp0   
          xData |= 0x01;         if (BIT1 (i) ^bit3 (i) ^bit5 (i) ^bit7 (i))   //CP1   
          xData |= 0x02;         if (BIT0 (i) ^bit1 (i) ^BIT4 (i) ^bit5 (i))   //cp2   
          xData |= 0x04;         if (BIT2 (i) ^bit3 (i) ^bit6 (i) ^bit7 (i))   //CP3   
          xData |= 0x08;         if (BIT0 (i) ^bit1 (i) ^bit2 (i) ^bit3 (i))   //CP4    
         xData |= 0x10;         if (BIT4 (i) ^bit5 (i) ^bit6 (i) ^bit7 (i))   //CP5   
          xData |= 0x20;                  if (BIT0 (i) ^bit1 (i) ^bit2 (i) ^BIT3 (i) ^BIT4 (i) ^bit5 (i) ^bit6 (i) ^bit7 (i)            
XData |= 0x40;                  Nand_ecc_precalc_table[i] =

XData;    }} int main () {    int i;     FILE *fp;     if (Fp=fope N ("C:\\ecc.txt", "wt+")) ==null) {        return 0;     }   
  Makeecctable ();
                  for (i=0; i<256; i++)     {  &nbs p;     if (i%16==0)         {     
       fprintf (FP, "\ n");        }         fprintf (FP, "0x%02X,", NAND
_ecc_precalc_table[i]);
   }          printf ("\ n");





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