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Here we will introduce the nfcon and nandflash control registers in the cloud6410cpu.

8.1 Overview
Recently nor Flash Memory price has increased and PR ice for SDRAM and a nand flash memory is moderatly placed.
The 6410 is equipped with an internal SRAM buffer called 'steppingstone '.
Generally, the boot code will copy NAND Flash content to SDRAM. using hardware ECC, the NAND Flash data
Validity will be checked. After the NAND Flash content is copied to SDRAM, main program will be executed on SDRAM.
To use NAND Flash, 'xselnand 'pin must be connected to high level.

8.2 features
NAND flash controller features include:

1. nand flash memory I/F: Support 512 bytes and 2kb page.
2. Software mode: user can directly access nand flash memory. For example this feature can be used in Read/Erase/program nand flash memory.
3. Interface: 8-bit nand flash memory interface bus.
4. Hardware ECC generation, detection and indication (Software correction ).

Hardware generation ECC, Software Correction
5. Support both SLC and mlc nand flash memory: 1-bit ECC, 4-bit and 8-bit ECC for NAND Flash.
(Recommend: 1bit ECC for SLC, 4bit and 8bit ECC for mlc nand flash)

Support nandflash of SLC and MLC: 1bit ECC for SLC nandflash, 4bit and 8bit ECC for MLC nandflash
6. SFr I/F: support byte/half word/word access to data and ECC data register, and word access to other registers
7. steppingstone I/F: support byte/half word/word access.
8. The steppingstone 8-kb internal SRAM buffer can be used for another purpose.

Other things won't be nonsense here. Let's take a look at the document.

Note:

Both 4bit and 8bit ECC modules can be used for only 512 bytes ECC parity code generation.

The 4-bit and 8-bit ECC modules can be used to generate an ECC check value for each read/write of 512 bytes of data.

4 bit and 8bit ECC modules generate the parity codes for each 512 byte. However, 1 bit ECC modules generate
Parity code per byte Lane separately.

4bit ECC modules generate Max 7 byte parity codes and 8 bit ECC modules generate 13 byte parity codes at each
512/24 bytes.

Each read and write of 512 or 24 bytes of data, the 4-bit ECC module generates a maximum of 7 bytes of ECC verification code, while the 8-bit ECC module generates a maximum of 13 bytes of verification code.

Let's take a look at the 8bit ECC codec:

8.8.5 8-bit ECC Programming Guide (encoding)
1. To use 8-bit ECC in software mode, set the MS glength to 0 (512-byte message length) and set the ecctype
To "01" (enable 8-bit ECC). ECC module generates ECC parit y code for 512-byte write data. In order to start
The ECC module, you have to write '1' on the init MECC (nfcont [5]) bit after cleaning the mainecclock
(Nfcont [7]) bit to '0' (unlock). mainecclock (nfcont [7]) Bit controls whether ECC parity code is
Generated or not.
Note. In 8bit ECC, mainecclock shoshould be cleared before initiating initmecc.
2. Whenever data is written, the 8bit ECC module generates ECC parity code internally.
3. After you finish writing 512-byte data (not include spare area data), the parity codes are automatically updated
To nf8mecc0, nfmecc1, nf8mecc2, nf8mecc3 Regi ster. You have to check encoding done at nfstat
Register. And set the mainecclock bit to '1' (LOCK). If you use 512-byte page size nand flash memory, you
Can program these values directly to spare area. However, if you use nand flash memory more than 512-
Byte page, You can't program immediately. In this case, you have to copy these par ity codes to other memory
Like dram. After writing all main data, you c an write the copied ECC values to spare area.
The parity codes have self-correctable information include parity code itself.
4. To generate spare area ECC parity code, set the msglength to 1 (24-byte message length), and set
Ecctype to "01" (enable 8bit ECC). 8bit ECC module generates the ECC parity code for 24-byte data. In
Order to initiating the module, you have to write '1' on the initmecc (nfcont [5]) bit after clearing
Mainecclock (nfcont [7]) bit to '0' (unlock ).
Mainecclock (nfcont [7]) Bit controls whether ECC parity code is generated or not.

Note. In 8bit ECC, mainecclock shoshould be cleared before initiating initmecc.
5. Whenever data is written, the 8bit ECC module generates ECC parity code internally.
6. When you finish writing 24-byte meta or extra data, the parity codes are automatically updated
Nf8mecc0, nfmecc1, nf8mecc2, nf8mecc3 register. You have to check encoding done at nfstat
Register. And set the mainecclock bit to '1' (LOCK). You can program these parity codes to spare area.
Parity codes have self-correctable information include parity code itself.

Part of the Translation: (for reference only)

8-bit ECC encoding: 1. To use 8-bit ECC, set msglength to 0 (512-byte message length) and set ecctypet to "01" (enable 8bit ECC ). The 8bit ECC module generates an ECC verification code after reading 512 bytes of primary data. To start working on an 8-bit ECC module, you must clear mainecclock (nfcont [7]) to 0 before setting initmecc (nfcont [5]) to 1. The mainecclock (nfcont [7]) Bit controls whether to generate the corresponding ECC verification code. Note: In 8bit ECC, mainecclock must be cleared first, and then set to 12 for initmecc. Once data is written, the ECC module of MLC generates the corresponding ECC verification code. 3. When you write 512 bytes of primary data (excluding the backup zone data), the corresponding ECC verification code will be automatically updated to nfm8ecc0, nfm8ecc1, nfm8ecc2, nfm8ecc3 register. You must check whether the encoding is complete in the nfstat register (Here it should be nfstat [7], I do not know why the 7bit IN THE nfstat register in the document is reserved, and the Samsung MLC
This bit is useful in BSP. In this case, you can think about it ). At the same time, set mainecclock to 1 to lock. If you use 512-byte nandflash storage, you can directly write the generated ECC verification code to the backup zone. If your nandflash storage exceeds the page size of 512 bytes, you cannot directly write the generated ECC verification code to the backup zone. In this case, you must copy the ECC verification code generated for every 512 bytes of primary data written to another memory, such as dram. After writing all the primary data (that is, one page of primary data), you can write the ECC verification code copied to other memory to the backup zone. This verification code carries the information for self-correction and the verification code value.

The rest of ECC reads and writes are basically the same, so we will not translate them here.

8.8.6 8-bit ECC Programming Guide (Decoding)
1. To use 8bit ECC in software mode, set the msglength to 0 (512-byte message length) and set the ecctype
To "01" (enable 8bit ECC). 8bit ECC module generates e CC parity code for 512-byte read data. In order
Initiating 8bit ECC module, you have to write '1' on the initmecc (nfcont [5]) bit after clearing
Mainecclock (nfcont [7]) bit to '0' (unlock ).
Mainecclock (nfcont [7]) Bit controls whether ECC parity code is generated or not.
Note. In 8bit ECC, mainecclock shoshould be cleared before initmecc
2. Whenever data is read, the mlc ecc m odule generates ECC parity code internally.
3. After you complete reading 512-byte data (not including spare area data), you must set the mainecclock
(Nfcont [7]) bit to '1' (LOCK) after reading parity codes. 8bit ECC module needs parity codes to detect
Whether error bits exists or not. So you have to read the ECC parity code of 512-byte main data right after
Reading the 512-byte data. Once the ECC parity code is read, 8bit ECC engine starts searching any error
Internally. 8bit ECC error searching engine needs mini mum 372 cycles to find any error. And set
Mainecclock bit to '1' (LOCK). eccdecdone (nfstat [6]) can be used to check whether ECC decoding is
Completed or not.
4. When eccdecdone (nfstat [6]) is set ('1'), nf8eccerr0 indicates whether error bit exists or not. If any
Error exists, you can fix it by referencing nf8eccerr0/1/2 and nfmlc8bitpt0/1 register.
5. If you have more main data to read, continue doing from step 1.
6. For Meta data error check, set the msglength to 1 (24-byte message length) and set the ecctype
"01" (enable 8bit ECC). ECC module generates the ECC parity code for 24-byte data. In order to initiating
8bit ECC module, you have to write '1' on the initmecc (nfcont [5]) bit after clearing the mainecclock
(Nfcont [7]) bit to '0' (unlock ).
Mainecclock (nfcont [7]) Bit controls whether ECC parity code is generated or not.
Note. In 8bit ECC, mainecclock shoshould be cleared before initmecc
7. Whenever data is read, The 8bit ECC module generates ECC parity code internally.

8. After you complete reading 24-byte, you must set the mainecclock (nfcont [7]) bit to '1' (LOCK) after read
Ing the parity code for 24-byte data. mlc ecc module needs parity codes to detect W hether error bits exists
Or not. So you have to read ECC parity codes right after reading 24-byte data. Once ECC parity code is read,
8bit ECC engine starts searching any error internally. 8bit ECC error searching engine needs minimum 372
Cycles to find any error. And set the mainecclock bit to '1' (LOCK). eccdecdone (nfstat [6]) can be used
Check whether ECC decoding is completed or not.
9. When eccdecdone (nfstat [6]) is set ('1'), nf8eccerr0 indicates whether error bit exist or not. If any

Error exists, you can fix it by referencing nf8eccerr0/1/2 and nf8mlcbitpt register.

Part of the Translation: (for reference only)

8-bit ECC decoding: 1. To use 8-bit ECC, set msglength to 0 (512-byte message length) and set ecctypet to "01" (enable 8bit ECC ). The 8bit ECC module generates an ECC verification code after reading 512 bytes of primary data. To start working on an 8-bit ECC module, you must clear mainecclock (nfcont [7]) to 0 before setting initmecc (nfcont [5]) to 1. The mainecclock (nfcont [7]) Bit controls whether to generate the corresponding ECC verification code. Note: In 8bit ECC, mainecclock must first clear 0, and then set 12 to initmecc. Once the data is read, the ECC module of MLC generates the corresponding ECC verification code. 3. After reading 512 bytes of primary data (excluding the backup zone data), read the verification code of the corresponding primary data zone, and then set mainecclock (nfcont [7]). the bit is 1, which locks the generation of ECC. The 8-bit ECC module needs this verification code to determine whether an error bit exists. Therefore, you must read the ECC verification code of the corresponding primary data zone after reading the 512-byte primary data. Once the ECC verification code corresponding to the primary data zone is read, the 8-bit ECC engine starts to look for errors. An 8-bit ECC error search engine requires at least 372 cycles to find existing errors. Set the mainecclock bit to 1 and lock it. Eccdecdone (nfstat [6])
It can be used to check whether ECC decoding is complete. 4. When eccdecdone (nfstat [6]) is set to 1, nf8eccerr0 indicates whether an error bit exists. If an error exists, you can use nf8eccerr0/1/2 and nfmlc8bitpt0/1 to correct the error. 5. If you have more master data to read, repeat the operation from the first step.

PS: Some registers in the original text are written incorrectly. You should pay attention to them when reading them.

The document of Samsung is really simple, and there are still many errors.

Note the following points:

When writing data to nandflash, each write of 512 bytes generates an ECC. Here we use 4 K pages, which are larger than 512 bytes. Therefore, we must save the generated ECC checksum, after a page (4 K) is written, write the ECC into the backup zone.

When reading data, each 512-byte master data is read, and an ECC is generated. In this case, ECC verification and correction are required. This is not the same as writing. Pay attention to this.

Register part:

The red circle is mainly used for registers and registers used by 8bit ECC.

This is the main register used. The next article will start the code section.