NET-Port Literacy II: A simple analysis of the principle of Mac and PHY composition

NET-Port Literacy II: A simple analysis of the principle of Mac and PHY composition 1. General

The following figure is a schematic diagram of the network port. The network port is composed of CPU, Mac and PHY. The DMA controller is usually part of the CPU and is placed here in order to indicate that the DMA controller may be involved in the network port data transfer.

For the above three parts, and not necessarily are independent of the chip, according to the combination of forms, can be divided into the following types: CPU integrated mac and PHY; CPU integrated mac,phy using independent chip; CPU does not integrate Mac with PHY,MAC and PHY using integrated chip;

In this case, choose Scheme II to further explain, because the CPU bus interface is very common, usually can be made like access to memory, no need to take out, and Mac and PHY between the Mii interface need to do some more explanation.

The diagram below is a screen structure diagram using scheme two. A dashed frame indicates that the CPU,MAC is integrated into the CPU. The PHY chip connects to the Mac on the CPU through the Mii interface.

The operation of the network port on the software is usually divided into the following steps: allocating memory for data sending and receiving; Initialize MAC registers; Initializes the PHY register (via MIIM); Start and send and receive; 2. MII

The Mii interface is a standard interface for Mac and PHY connections. Because the manufacturers use the same interface, users can according to the required performance, price, the use of different models, or even the PHY chip of different companies.

The data that needs to be sent is realized by two sets of buses in the MII interface. The configuration information of PHY chip registers is realized through a group of serial bus MII, namely Miim (MII Management).

The following table lists some of the main pins in the MII bus

PIN Name	Direction	Description
Txd[0:3]	Mac to Phy	Transmit Data
Txen	Mac to Phy	Transmit Enable
Txclk	Mac to Phy	Transmit Clock
Rxd[0:3]	Phy to Mac	Receive Data
Rxen	Phy to Mac	Receive Enable
Rxclk	Phy to Mac	Receive Clock
Mdc	Mac to Phy	Management Data Clock
Mdio	Bidirection	Management Data I/O

Miim has only two lines, the clock signal MDC and the data line Mdio. Both the read and write commands are initiated by the MAC, and PHY cannot send the message to the Mac via Miim. Since MIIM can only have Mac initiation, we can operate only on Mac registers. 3. DMA

Sending and receiving data is always time-consuming and laborious, especially for networked devices. CPU does these things obviously not appropriate. Since it's data removal, the easiest way to do this is to let DMA do it. After all, the best is the professional.

So the CPU to do is simple. Just tell the DMA start address and length, and the rest will be done automatically.

Usually in the Mac there will be a set of registers dedicated users to record the data address, tbase and rbase, the CPU according to the format of the Mac to put the data, the launch of the MAC data can be sent. The startup process often uses register tstate. 4. MAC

There are two sets of registers with the Mac on the CPU. A set of user data to send and receive, corresponding to the above DMA; a group of user Miim, the user configures PHY. Two sets of registers are all on the CPU, configured in the same way as other CPU registers, directly read and write. The forwarding of the data is done through DMA. 5. PHY

The chip is a 10m/100m Ethernet network chip

PHY Chip has a set of register users to save the configuration and update the status. The CPU cannot access this set of registers directly, and it can only be accessed indirectly through the MIIM Register group on the Mac. At the same time PHY chip is responsible for the completion of Mii bus data and media interface data forwarding. This forwarding is done automatically based on the register configuration and does not require external intervention.

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