Network byte order problem in FPGA for network communication

Send character ABCD on PC software
Grab the bag on the shark

Receiving PIN analysis from FPGA network using Logic Analyzer

Data is received and stored in RAM with a bit width of 8bit
Read 32bitUDP data from RAM for

64636261

According to the above phenomenon,
Before there was an understanding deviation,
The so-called big-endian small end is a reading order different,
For UDP data segments, the data composition format is determined by both parties,
Only the head of the protocol, etc., is organized according to the big end, in order to communicate in different CPU systems,
For example, the above is the ABCD, then the UDP data segment is sent according to ABCD,
Data into the FPGA
stored in 8bit width of RAM (address small to large)
0x61
0x62
0x63
0x64
Nios Soft core CPU is also small end, so
When these 4 bytes are read to a 32bit unsigned variable
Like alt_u31 buff.
buff=0x64636261;
High address data placed at high level
If the buff is cast to (ALT_U8) Buff output
The output is 0x61, which is also a way to prove that Nios is a small end.

So overall, the network data is not really what the size of the end, the size of the end is only relative to the hardware CPU or network equipment,
That is, how the transmitted data is represented,

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Network byte order problem in FPGA for network communication