Network literacy II: a simple analysis of MAC and PHY composition principles

 

1. General

A brief diagram of the network port structure. the network port consists of three parts: CPU, Mac, and PHY. the DMA controller is usually a part of the CPU. the dotted line is placed here to indicate that the DMA controller may be involved in data transmission at the network port.

These three components are not necessarily independent chips. They can be divided into the following types based on the combination:

1. The CPU is integrated with Mac and PHY;
2. The CPU is integrated with Mac, and the PHY uses an independent chip;
3. The CPU is not integrated with Mac and PHY, while Mac and PHY are integrated with chips;

In this example, solution 2 is used for further description. Because the CPU bus interface is very common, it is usually made accessible like the access memory, the MII interface between MAC and PHY requires more instructions.

The network port structure of solution 2 is used. The virtual box indicates the CPU, and the Mac is integrated into the CPU. The PHY chip connects to the Mac on the CPU through the MII interface.

In software, the network port operations are generally divided into the following steps:

1. Allocate memory for sending and receiving data;
2. Initializes Mac registers;
3. Initialize the PHY register (through miim );
4. Start sending and receiving;

2. MII

The MII interface is the standard interface for connecting Mac and PHY. Because manufacturers use the same interface, users can use different models or even company's PHY Chips Based on the required performance and price.

The data to be sent is implemented by sending and receiving two groups of bus in the MII interface. The configuration information of the register of the PHY chip is implemented by a group of serial bus in the MII, that is, miim (MII management ).

The following table lists the main pins in the MII bus.

Pin name	Direction	Description
Txd [0: 3]	Mac to phy	Transmit data
Txen	Mac to phy	Transmit enable
Txclk	Mac to phy	Transmit clock
Rxd [0: 3]	Phy to Mac	Receive data
Rxen	Phy to Mac	Receive enable
Rxclk	Phy to Mac	Receive clock
MDC	Mac to phy	Management Data clock
Mdio	Bidirection	Management data I/O

The miim has only two lines, namely the clock signal MDC and the data line mdio. all read and write commands are initiated by Mac, and PHY cannot send messages to MAC through miim. since miim can only be initiated by Mac, we can operate only the registers on Mac.

3. DMA

Sending and receiving data is always time-consuming and laborious, especially for network devices. the CPU is obviously not suitable for these tasks. since it is data migration, the simplest way is to let DMA do it. after all, professional is the best.

In this way, the CPU is easy to do. You only need to tell the DMA start address and length, and the rest will be completed automatically.

Generally, in Mac, there will be a set of registers for users to record the data addresses, tbase and rbase. After the CPU puts the data in the format required by Mac, start MAC data transmission. the tstate register is often used during the startup process.

4. Mac

The CPU has two sets of registers and Mac. send and receive a group of user data, corresponding to the above DMA; a group of user miim, the user configures the phy. because the two sets of registers are on the CPU, the configuration method is the same as that of the registers on other CPUs. data Forwarding is completed through DMA.

5. phy

This chip is a 10 m/100 M Ethernet port Chip

The PHY chip has a set of registers that the user saves and updates the configuration. the CPU cannot directly access this set of registers. It can only achieve indirect access through the miim register group on Mac. at the same time, the PHY chip is responsible for forwarding MII bus data and media interface data. the forwarding is automatically completed based on the register configuration without external intervention.