Bcm56133 chip supports four QoS modes: Port-ID-based, MAC address-based, 802.1 p-based, and DiffServ-based priority settings.
Registers based on 802.1 p and DiffServ priority settings are quickly found in register definitions;The Port-based priority setting register is in the 802.1Q VLAN section..
ConfigurationQoS pause enable register registers will be encountered during the configuration process, and later I will understand its role:
(Before departure: Normally, the Ethernet Switching Control Circuit for storage and forwarding has three buffer modes: Port input buffer, shared central buffer, and port output buffer. When the data transmission rate of the sender and receiver does not match, in order to prevent the data of the high-speed sender from flooding the low-speed receiver, the traffic control mechanism must be used to enable the sender to fill the buffer zone of the receiver, stop sending data frames. When the buffer zone is empty, send data frames again. To achieve traffic control at the data link layer, you can adjust the transmission rate of connected devices, solve congestion problems, and reduce Frame loss .)
1. Ethernet traffic control technology
The data link layer is divided into Logical Link Control Sub-layer, MAC control sub-layer, and Media Access Control (MAC) Sub-layer. The MAC control sub-layer is an optional sub-layer, which specifies a universal full-duplex traffic control structure framework. The carrier listens for Multi-Channel Access/conflict detection (CSMA/CD) the algorithm implements half-duplex traffic control.
1.1. Traffic Control Technology for half-duplex Networks
When the Ethernet Switching Control Circuit port is in half duplex mode, the CSMA/CD algorithm that complies with the IEEE 802.3 protocol can implement implicit traffic control, back Pressure Technology (backpressure) is used to prevent buffer overflow. Before the sender's data arrives, a certain action is taken to prevent the sender from sending data.
Back Pressure technology is a pseudo-collision signal (false collision signal) Technology sent by the switching control circuit. Back Pressure technology is usually implemented based on the percentage of used buffer capacity. When the used buffer capacity reaches a preset proportion, the port generates a blocking signal based on this threshold, when the idle buffer capacity exceeds another low proportion, the port will cancel the blocking signal. In the CIDR block where the congestion port is located, the transmission of blocking signals can enable all ports in the CIDR block to detect the conflict and transmit data frames after the blocking signal ends, in this way, more collisions are blocked, and data transmission is temporarily suspended to free up the buffer space. (The implementation method is not described here)
1.2 full duplex Network Traffic Control Technology
In a full-duplex network, switching control circuit ports do not detect conflicts and ignore carrier listening that can be transmitted with delay. Therefore, backpressure technology is not used to solve congestion and explicit traffic control mechanisms are required, enables the switching control circuit to block sites in the congested state.
The 802.3 protocol provides a full-duplex traffic control structure framework for the Mac control sub-layer. The MAC control sub-layer is an optional function between the Logical Link Control Sub-layer and the Media Access Control Sub-layer, the position of the MAC control sub-layer in the OSI system is shown below.
OSI reference model
Application Layer
Presentation Layer
Session Layer
Transport Layer
Network Layer
Data Link Layer
(From top to bottom, it can be divided into: A, LLC -- Logical Link Control B,MAC Control-- (Optional)
C. Mac-Media Access Control)
Physical Layer
To prevent buffer overflow, the switching control circuit can use the MAC control sub-layer to control the operation of the Ethernet Media Access Control Sub-layer. When the used buffer capacity reaches a preset threshold, the port sends a request to the end of the full-duplex link to stop sending data. This request is implemented through the control frame generated by the MAC control sub-layer.
Similarly, the port can receive Control Frames generated by the MAC control sub-layers of other sites. The control frames are sent in the customer's data frame stream, and the receiver will separate the Control Frames according to the content of the frames, the traffic control module is submitted to the MAC Control sublayer. The traffic control module parses the content of the control frame, extracts the control parameters in the frame, and determines the time to suspend sending based on the control parameters.
In the full-duplex MAC control framework, the traffic control mechanism is implemented through the pause function. The pause function prevents unnecessary Frame loss when the buffer overflow occurs due to transient overload. The pause operation implements a simple stop-equality flow control mechanism. If a port wants to stop frame receiving, it can send a pause frame with parameters, which indicates the waiting time before the end of the full-duplex link starts sending data. When the end of a link receives a pause frame, it stops sending data within the time specified by the parameter. When the specified time exceeds or the port traffic control status is released, the original congestion port resends the pause frame with the operation parameter 0, and the other end of the link continues to send data frames from the paused position.
MAC control frame is an Ethernet frame conforming to the 8808 protocol and can be identified by its unique type domain identifier (0 x. The transmission and receipt of MAC Control Frames over the network are similar to those of data frames. In addition to the forward code and frame start character, the minimum frame length of an Ethernet frame is 64 bytes ). The first two bytes of the MAC Control Frame indicate the MAC control operation code, indicating the frame request control function. Currently, the Protocol only defines one operation code, namely, the pause operation. The operation code is 0x0001. The operation code is the required parameter for the operation. The parameter only uses two bytes of the data field, and the rest of the data field will be filled with 0.
Pause frame format(The frame length is 64 bytes ):
Forward code (7 bytes) +
Destination Address (6 bytes) +
Source Address (6 bytes) +
Type (2 bytes) +
Frame start character (1 byte) +
Operation Code (2 bytes) +
Operation parameters (2 bytes) +
Reserved (42 bytes) +
Verification sequence (4 bytes)
2. Implementation of full-duplex Traffic Control Mechanism of Switching Control Circuit
2.1. Pause operation implementation
After the two links enable traffic control through automatic negotiation, the link port can generate pause frames, and recognize pause frames and respond to stop-and other requests when receiving frames, switching Control Circuit pause has three main implementation aspects.
1st: Pause frames should be sent in a timely manner. The Ethernet Switching Device sends data frames in sequence and inserts pause frames when the buffer zone overflows. Pause frames may be delayed due to waiting in queue for sending. Therefore, pause frames should have the sending priority. If the data frame is being transmitted before the pause frame is sent, the pause frame must wait until the transmission of the current data frame is completed and can be sent only after the frame interval.
2nd: Identify the received pause frames. The recognition process requires 512-bit link transmission time, which is the time required to completely receive 64-byte pause frames. The receiving port performs protocol analysis on all received frames and checks the destination address, frame type, MAC control operation code, and frame verification sequence of the received frames in combination with the pause frame format, determine whether a correct pause frame is received. Multiply the extracted pause time by the 512-bit link transmission time to get the port pause time. If a pause frame with Zero pause time is received, the port traffic control status is removed.
3rd: reasonably set the time to send traffic control requests. Because the full-duplex link has transmission latency and response latency, after a pause frame is sent, the other party cannot immediately stop sending data frames. The sender must consider the maximum amount of data that can be received after a pause frame is sent to avoid Buffer Overflow. The Ethernet Switching Control Circuit in this design supports 10 m/m link transmission. In the worst case, consider the following factors:
(1) A maximum data frame (1 536 bytes) is being sent before the pause frame is sent );
(2) The time spent sending pause frames is 512-bit link transmission time;
(3) The sending frame interval is 96-bit link transmission time;
(4) The recipient is starting to send a maximum data frame (1 536 bytes) while parsing the pause frame );
(5) the receiving frame interval is 96-bit link transmission time;
(6) The round-trip transmission delay time of the link.
Based on the above factors, after a traffic control request is sent, about 3-2 K bytes of data will be waiting for receiving and caching. Pause frames can terminate the transmission of the data frame of the other link. When designing the buffer capacity and selecting the traffic control threshold, consider these latency factors to effectively implement the traffic control mechanism to prevent Frame loss.
2.2 Implementation of a buffer Policy
Although 802.3 has defined a traffic control mechanism, when traffic control is enabled depends entirely on the supplier or user. There can be different Methods Based on the implementation complexity, such as setting the pause time in the pause frame and the buffer capacity of the switching control circuit.