With the advent of the NI pxie-5644r vector signal transceiver (VST), ni reshaped the concept of the instrument by introducing the flexibility of the user-programmable FPGA into the RF instrument.
1. High performance and revolutionary design
NI pxie-5644r VST combines typical RF I/O functions in a vector signal analyzer (VSA) and vector signal Generator (VSG) with NI or user-defined functions for signal processing and control in a field Programmable gate array (FPGA). The RF input and RF outputs include a separate local oscillator (LO), a frequency range of up to 6 GHz, and an instantaneous bandwidth of up to a MHz. NI pxie-5644r belongs to a single 3-Slot PXI Express module (see Figure 1). Multi-input multi-output (MIMO) configurations can be created by using multiple VST modules in a single PXI express chassis.
Figure 1:ni PXIE-5644R Hardware front panel
What is the most striking feature of NI pxie-5644r? No doubt, of course, it is such a small size that it can achieve very high performance. By leveraging advanced calibration and wideband digital correction, NI PXIE-5644R VST can meet the performance needs of research-level instruments with its incredibly small size. The faster test time and flexibility offered by user-programmable FPGAs makes NI pxie-5644r more suitable for RF characterization, validation and validation, and product testing.
In addition to high performance and small size features, the most revolutionary feature of NI PXIE-5644R VST is the use of a user-programmable Xilinx Virtex-6 FPGA, which supports programming with LabVIEW FPGA modules. The FPGA connects to the VSA and VSG baseband I/Q data with a digital I/O line with 24 data rates up to Mbit/s. The powerful combination of RF technology, high-speed digital I/O technology and FPGA technology enables NI pxie-5644r to handle many applications such as true-to-test device (DUT) control, custom triggering, power level servo, software defined radio and channel emulation.
2. FPGA Base Card Architecture
The NI pxie-5644r FPGA base card includes Xilinx Virtex-6 FPGA, baseband clock circuit, analog-to-digital converter (ADC), D/A DAC, digitally I/O line with programmable function (PFI 0), digital I/O connector, PCI Express interface, PXI triggers, DRAM, and SRAM.
Figure 2:ni pxie-5644r FPGA base card block diagram
Xilinx Virtex-6 FPGA
NI pxie-5644r contains a Xilinx Virtex-6 lx195t FPGA for system configuration, digital data movement, and digital signal processing. The FPGA is directly connected to the ADC, DAC, PCI Express bus, DRAM, SRAM, PFI 0, digital I/O, and PXI triggers, allowing custom programming to meet the requirements of various types of applications.
Reconfigurable FPGA Resources
The Xilinx Virtex-6 lx195t FPGA contains the following resources.
Supports LabVIEW FPGA programming
The Xilinx FPGA for NI PXIE-5644R fully supports programming with the LabVIEW FPGA module. Because LabVIEW can easily represent parallelism and data flow, it is well suited for FPGA programming. Therefore, for the traditional FPGA design of new and old users, can effectively utilize the functionality of reconfigurable hardware.
NI provides LabVIEW sample projects and instrument Design VI for NI pxie-5644r to help users quickly design and perform first-time measurements. Instrument Design VI allows users to modify the LabVIEW code for FPGA and processor hierarchies (such as PC and RTOs) and classify them by functional type, such as configuration, acquisition, generation, digital signal processing (DSP) and Synchronization (3). To learn more about NI pxie-5644r vst software, see the VST Software Architecture white paper or watch VST network video.
Figure 3: LabVIEW Sample project and instrument design for NI pxie-5644r hardware VI
NI pxie-5644r contains multiple clocks within the FPGA. The master clock is a sampling clock that can be used for ADCs, DACS, and related FPGA logic.
The sampling clock frequency is at + MHz and is exported by a phase-locked loop (PLL). You can choose to use an internal Tcxo, NI 5644R REF in front panel connector, or PXI_CLK 10 as a reference signal for the PLL. As shown in 4, the sampling clock can also be used as a reference signal for the RF in and RF out internal lo circuitry. Although the sampling clock frequency is fixed at + MHz, high-resolution I/Q data rates can be achieved through fractional interpolation and fractional decimation of DSP VI inside the FPGA.
Figure 4:ni pxie-5644r Clock architecture
The following table lists the clocks in the FPGA. In addition to this clock, the LabVIEW FPGA allows the user-defined frequency clock to be derived.
ADCs and DACs
NI PXIE-5644R uses dual-channel 16-bit ADCs and DACs. The ADC and DAC use a clock frequency of ms/s, which provides a complex bandwidth of up to MHz and is automatically synchronized with the sampled clock domain inside the FPGA. This approach facilitates full synchronization of the ADC and DAC in the same clock domain, enabling deterministic delays between receive and transmit. The RF in and RF out IQ data streams are in the same clock domain of the FPGA. Synchronization and deterministic latency make it easier to program real-time testing and embedded applications.
PFI 0 is a 3.3 v LVTTL, bidirectional Universal digital I/O port. PFI 0 is typically used for trigger input or tick/event output. However, since the PFI 0 I/O cache is directly connected to the FPGA, the functions of PFI 0 can be configured by LabVIEW FPGA programming to meet specific application requirements.
The VHCDI port allows access to NI pxie-5644r digital I/O. A total of 24 bidirectional Lvttl digital I/O lines are included, each with 4 lines (6 ports in total), and can be individually configured for each port. The digital I/O connector also includes clock input and clock output lines, as well as PFI 1 and PFI 2 lines that can be used for triggering or additional bidirectional digital I/O. Because the cache of digital I/O is directly connected to the FPGA, the functions of a single digital I/O port can be configured to meet specific application requirements through LabVIEW FPGA programming.
Cables and Accessories
NI offers a wide range of cables and accessories that are compatible with digital I/O connectors. Note that the cables and accessories use custom pins that match the NI pxie-5644r digital I/O and can maintain a 50 ohm transmission line environment. It is not recommended to use other VHDCI cables.
DRAM and SRAM
The NI pxie-5644r consists of two dram blocks, each of which is up to a maximum data rate of 2.1 GB/s, and each DRAM block can be accessed individually through the FPGA. The DRAM block is of a common type, but is typically used to store waveforms to be generated or captured waveforms.
Includes 2 MB of on-board SRAM with a maximum read and write data rate of two MB/s, respectively. SRAM is a common memory that is typically used to store multiple hardware configurations that can be applied directly from the FPGA without using a host.
PCI Express Interface
The NI pxie-5644r contains a generation of X4 PCI Express interfaces for DMA transfer, programmable I/O, and Point-to-point data flow.
3. Receiver Architecture
The NI pxie-5644r includes a 0 differential RF receiver, also known as a synchronous, 0 if or direct down-conversion receiver. In a 0 differential receiver, the input RF signal is passed to the mixer, which is similar to a traditional heterodyne receiver, such as a receiver in NI PXIe-5665 and Ni pxie-5663e VSA. However, unlike an heterodyne receiver, the LO frequency in the 0 differential receiver is equal to or closer to the frequency of the input RF signal, resulting in a DC center or low if signal, such as 10 or MHz.
The input signal is mixed with the baseband and split into the same phase (I) and quadrature (Q) components, where the carrier is in the same phase and is offset 90 degrees respectively. The I and Q path signals are then digitized separately and the I and Q data are obtained. The final software combines the I and Q data streams and displays the original signal. Figure 5 shows a brief block diagram of the 0-or 0-if architecture.
Figure 5: Basic block diagram of the 0 differential (0-IF) architecture
0 Differential (0 medium frequency) receiver benefits
Compared to traditional heterodyne architectures, the 0 difference architecture offers many advantages, such as simplified design, low cost, low power, and more choice, and can be used to separate adjacent channels where the signal overlaps. Other benefits include higher bandwidth, simplified design through a single lo, compact design to provide smaller package sizes, and more. The following sections describe each of these benefits in detail.
1. Bandwidth. The receiver with a single ADC has an actual upper limit of the signal bandwidth, which is 40% of the clock frequency. Using the same sampling clock frequency, the 0 differential architecture includes two ADCs, which allows for a double bandwidth of 80% of the sampled clock frequency. In general, better spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) performance can be achieved with ADCS that support a lower sampling clock frequency. The 0 differential receiver allows for wider bandwidth without compromising ADC performance, while for receivers with only a single ADC, the ADC performance is reduced in this condition.
2. Single local oscillator (LO). Since multichannel test systems are becoming more and more important in multi-input multi-output (MIMO) applications, shared lo becomes a must-have requirement. Compared to using multiple lo in a traditional heterodyne architecture, the 0-difference architecture only needs to share a single lo to reduce costs and greatly reduce the complexity of system configuration.
3. Compact design. Compared to the Heterodyne architecture, the 0-difference architecture uses a simpler RF design. Less lo signal, no large, expensive RF and if filters, and the 0 differential architecture requires fewer conversion stages, making the design more streamlined.
0 Differential (0-if) receivers face the challenge
Although the zero-difference architecture has many advantages, there are drawbacks such as the inability to implement envelope detection. NI PXIE-5644R solves this problem by using orthogonal detection and digital signal processing.
The DC offset is another challenge for the 0 if architecture. Any signal mixed to 0 Hz in the ZIF structure will cause the spectral component of the DC, which is present in the middle of the data acquisition instantaneous bandwidth. A spectrum consisting of the data collected and the frequency offset of the instantaneous bandwidth will display the repeating DC offset component in the middle of each collected data. DC offset zeroing can be achieved by applying offsets in the digitized I and Q data streams. Each lo frequency must apply a separate zeroing operation, which can be done automatically when the NI pxie-5644r self-calibration process is run.
Receiver Signal Path
The NI pxie-5644r Receiver is designed with the top-level architecture shown in 6. This block diagram shows the calibration synthesizer, an optional high power attenuator, an optional low-power signal amplifier, an out-of-band filter, additional gain and attenuation signal conditioning, and a mixer (three) for demodulation based on frequency selection.
Figure 6:ni pxie-5644r receiver block diagram
Select filter banks contain 8 different paths with low-pass or bandpass filters. The filter allows the receiver to filter out excess noise, allowing the receiver to only process signals within the desired range. After the selected filter and other signal conditioning, the RF signal will be sent to one of the demodulator (three total) depending on the frequency. Each demodulator can be used to specify bands to optimize gain and phase.
The receiver path contains multiple solid-state attenuators that provide attenuation over a DB and Support 1 db step changes. The RF input is AC-coupled, and three switchable gain amplifiers and a preamplifier can be used to extend the dynamic range and improve the noise index.
The internally supplied low phase noise lo (local oscillator) connects multiple down converters to a single lo source. Using the same lo source is useful for signal acquisition applications with phase coherence, such as multi-input multi-output (MIMO) systems. When this configuration is used, each NI pxie-5644r RF channel that shares the same lo will be adjusted to the same RF frequency.
The baseband signal of the down-conversion is transmitted directly to the internal ADC channel of the NI pxie-5644r. The ADC channel will digitize the baseband analog signal according to the MS/S and 16-bit dynamic range, passing the results to the onboard FPGA for subsequent processing, and finally to the host.
The NI pxie-5644r receiver includes a single-stage direct conversion (I/q) down-converter. The RF signal is converted from the configured Lo frequency to the DC, where the baseband signal can be digitized for subsequent processing. The architecture allows for wide instantaneous bandwidth while ensuring efficient mirror-frequency rejection and minimizing lo leakage. Mirror frequency rejection and lo leakage performance can be achieved with wideband quadrature correction, the receiver path is optimized and can be used as a vector signal analyzer for wideband demodulation
Low if mode and in-band re-adjustment
The low if receiver is another type of receiver using the IQ demodulator with the same block diagram as the 0 if receiver shown in Figure 5. In a 0 if receiver, the LO frequency is within the frequency range of the modulated signal, while the lo frequency of the low if receiver is outside the modulation signal range. This causes the DC component to no longer be in the lower frequency range. There will be no partial DC-related derogations, such as DC offset, F/f noise, and baseband harmonics in some cases.
Operation of the NI pxie-5644r in low if mode enables the combination of the two functions of LO modulation and digital frequency domain shift. Generating or acquiring the required signal from the carrier at a digital shift frequency avoids the problem of lo leakage in the direct conversion structure. At the cost of this approach, the maximum bandwidth of the low if receiver is half of the 0 if receiver using the same ADC sample rate. The NI pxie-5644r can support complex instantaneous bandwidths up to a maximum of 4 MHz and the additional complex bandwidth allocated to digital frequency correction for an extra high-speed of up to a few. An additional frequency shift causes the available MHz bandwidth to be reduced to (80/2)-(x-2) MHz, where x represents the requested digital frequency shift.
4. Transmitter Architecture
The RF transmitter architecture on NI pxie-5644r VST consists of 2 modulators, a filter bank, and an additional signal conditioning module. The top-level block diagram is shown in 7.
Figure 7:ni PXIE-5644R transmitter block diagram
Signal path of the transmitter
The 2 modulator in NI pxie-5644r is the same as the modulator used in NI pxie-5673e VSG, and its phase and gain balance are optimized for different frequencies. The filter banks of the NI PXIE-5644R RF transmitter are the same as the filter banks used in the RF receivers, with 8 paths with low-pass or bandpass filters, as shown in 7.
The filtered RF signal enters the cascade signal conditioning module, which includes 3 programmable attenuators, an optional amplifier, and 2 fixed amplifiers. Finally, depending on whether the transmission path needs to be calibrated, the RF signal is switched to the RF output or calibrated to the output front panel connector.
The NI pxie-5644r RF transmitter path contains 1 single-stage direct conversion (I/q) upconverter that can convert baseband signals from DC to a configured LO frequency RF signal. This architecture enables wide instantaneous bandwidth while ensuring efficient mirror-frequency rejection and minimal lo leakage. The high performance of both mirror-frequency suppression and lo leakage is achieved through wideband quadrature correction. The path is optimized and can be used as a CW generator or VSG wideband modulation.
The transmitter path contains 4 solid-state attenuators that provide attenuation over a maximum of three DB and Support 1 db step changes. When a high power signal needs to be generated, 1 additional adjustable gain amplifiers are used.
The Low Phase noise lo (local oscillator) provided internally by the transmitter path can connect multiple upconverter to a single lo source. For MIMO systems, using the same Lo source is useful for generating phase-coherent signals. When this configuration is used, each channel of NI pxie-5644r rf that shares the same lo will be adjusted to the same RF frequency.
Average power and crest factor considerations
The crest factor represents the power change between the peak signal power and the mean RMS (RMS) power. The sine signal used in CW mode has a crest factor of 3 db, which means that the average RMS power of the sine signal is 3 db less than the peak power. Modulated signals (especially OFDM) have a larger crest factor, about ten db to three db.
When configured as a signal generation device, it is important to consider both the average RMS power and the crest factor. The NI pxie-5644r supports a maximum average power output of 6 dbm and a crest factor of up to a few db. After the average power of 6 dbm is exceeded, the device will not be able to ensure that it is calibrated or maintained linear. In particular, it is important to note that when the average power is set to exceed 6 dbm and the crest factor of the signal is still set to greater than or equal to-db, the reverse power protection circuitry of the NI pxie-5644r may occur severely saturated or enabled.
5. Synthesizer local oscillator (LO) architecture
The NI pxie-5644r is available in the frequency range of 6 GHz and offers adjustment accuracy less than 1 Hz. The modulation accuracy includes the LO step size and the frequency shift DSP implemented on the FPGA.
Two lo stepping modes:
1. Integer step mode includes 4, 12, and MHz steps
2. The staged step mode includes a range of khz steps. This mode provides greater spacing but also generates more clutter signals, which ensures that the indicator is met.
The NI pxie-5644r synthesizer Lo First provides a three-MHz clock input phase-locked loop (PLL) that includes 3 vector control oscillators (VCOs) of 2 to 2.5 GHz, 2.5 to 3 GHz, and 3 to 4 GHz, respectively. If the desired output signal is less than 4 GHz, the current signal will be switched to the divider. Similarly, if the desired end signal is 4 to 6 GHz, the current signal will be switched to the multiplier (2 multipliers). Next, enter a filter group with an extra divider to remove the harmonics when needed.
After a certain gain is set, the signal is switched to an internal or external oscillator, which is used for MIMO applications that require phase coherence. To improve the performance of the MIMO configuration, the LO path can also be calibrated by calibrating the ADC before exporting. As shown in 8, the LO signal will be entered into a filter bank containing a low-pass and band-pass filter, which is the same as the filter used in the NI pxie-5644r RF receiver and transmitter.
Figure 8:ni pxie-5644r synthesizer Lo top-level block diagram
When the input RF signal is mixed with lo, the signal will contain the spectral edge from the lo, so it is important that the LO has good spectral purity. Band VSA typically uses an off-the-shelf integrated synthesizer, often less effective than a conventional discrete synthesizer. The NI pxie-5644r can be used in wideband instrument designs and is characterized by the ability to create a traditional discrete synthesizer from scratch. This approach allows NI pxie-5644r to achieve good measurement performance across all frequency ranges of the instrument.
The NI pxie-5644r includes the following three different PLL bandwidth options, which differ in phase noise and settling time.
1. High bandwidth-lower frequency settling time (+ us) and higher phase noise
2. Medium bandwidth-Medium settling time (US), phase noise similar to low bandwidth option, low bandwidth option is optimized for narrowband (at or less)
3. Low bandwidth-optimized phase noise and higher frequency settling time (1 ms)
When measuring RF standards (such as 802.11AC and LTE), it is generally advisable to use the medium bandwidth option. However, if you do not need to consider adjusting the speed, you can choose the low bandwidth option. High bandwidth options are used for high-speed FM. Figure 9 shows the phase noise for the different PLL bandwidth options. Figure 10 shows the phase noise at different frequencies using only the medium bandwidth option.
Figure 9: Measured 2.4 GHz phase noise and cyclic bandwidth
Figure 10: Phase noise measurement of the following frequencies using the Medium PLL bandwidth option: 1 GHz, 2.4 GHz, and 5.8 GHz
Each NI pxie-5644r board is factory-independent and precisely calibrated for frequency and amplitude response, each containing a calibration certificate for verifying the NIST traceable accuracy level. External Factory calibration Adjusts the frequency reference, internal Lo path gain, external lo path gain, RF input gain, and RF output gain. For long-term compliance with NI pxie-5644r, it is recommended to use factory calibration for one year (or two years in a wider specification).
NI pxie-5644r calibration relies on a fixed path between the RF input and the RF output. The path can be connected using the Sma-sma half-hard cable to connect the calibration input (Cal in) and the calibrated output (Cal out) front panel connector. Do not release or remove the cable from the front panel of the device, otherwise the self-calibration function will be affected.
In addition, self-calibration is recommended when the ambient temperature changes beyond 5 degrees Celsius (5°c). Temperature fluctuations can reduce the performance of several technical indicators of NI pxie-5644r. Perform self-calibration to compensate and optimize performance based on ambient temperature. Self-calibration corrects the temperature by adjusting the following NI pxie-5644r parameters:
. Lo Path gain
. RF Input Gain
. RF Output Gain
. RF Input Lo Leakage
. RF Output LO Leakage
. RF Input Mirror Frequency rejection
. RF output mirror-frequency rejection
The calibration synthesizer provides a stable amplitude by means of an amplifier with a stable frequency and low distortion. The calibration table on the device will simultaneously scan the frequency and power while also including the frequency vector calibration. Advanced calibration technology is one of the main reasons for NI pxie-5644r to achieve development-level instrument performance with small dimensions.
NI pxie-5644r vector Signal Transceiver hardware architecture