# Include <stm32f10x. h>
# Include "SYS. H"
// Sets the offset address of the vector table.
// Nvic_vecttab: Base Address
// Offset: Offset
// Check OK
// 091207
Void my_nvic_setvectortable (u32 nvic_vecttab, u32 offset)
{
// Check the validity of parameters
Assert_param (is_nvic_vecttab (nvic_vecttab ));
Assert_param (is_nvic_offset (offset ));
SCB-> vtor = nvic_vecttab | (offset & (u32) 0x1fffff80); // sets the C vector table offset register.
// Used to identify whether the vector table is in the code or RAM Zone
}
// Set the objective C group
// Nvic_group: group Objective C 0 ~ 4. Five groups in total
// Check OK
// 091209
Void my_nvic_prioritygroupconfig (u8 nvic_group)
{
U32 temp, temp1;
Temp1 = (~ Nvic_group) & 0x07; // obtain the last three digits
Temp1 <= 8;
Temp = SCB-> aircr; // read previous settings
Temp & = 0x0000f8ff; // clear the previous Group
Temp | = 0x05fa0000; // write key
Temp | = temp1;
SCB-> aircr = temp; // sets the group.
}
// Set objective C
// Nvic_preemptionpriority: preemption priority
// Nvic_subpriority: Response priority
// Nvic_channel: interrupt ID
// Nvic_group: interrupt group 0 ~ 4
// Note that the priority cannot exceed the set group range! Otherwise, unexpected errors may occur.
// Group Division:
// Group 0-0 preemptible priority, 4-bit response priority
// Group: 1-bit preemption priority, 3-bit response priority
// The Group has two-digit preemptible priority and two-digit response priority.
// The group has three-digit preemption priority and one-digit response priority.
// Group 4-4 preemptible priority, 0-bit response priority
// The principle of nvic_subpriority and nvic_preemptionpriority is that the smaller the value, the higher the priority.
// Check OK
// 100329
Void my_nvic_init (u8 nvic_preemptionpriority, u8 nvic_subpriority, u8 nvic_channel, u8 nvic_group)
{
U32 temp;
U8 ipraddr = nvic_channel/4; // each group can only store four addresses.
U8 iproffset = nvic_channel % 4; // The offset in the group
Iproffset = iproffset * 8 + 4; // obtain the exact offset position.
My_nvic_prioritygroupconfig (nvic_group); // sets the group
Temp = nvic_preemptionpriority <(4-nvic_group );
Temp | = nvic_subpriority & (0x0f> nvic_group );
Temp & = 0xf; // retrieve four lower bits
If (nvic_channel <32)
Nvic-> Iser [0] | = 1 <nvic_channel; // enable the interrupt bit (if you want to clear it, the opposite operation is OK)
Else extends C-> Iser [1] | = 1 <(NVIC_Channel-32 );
Nvic-> IPR [ipraddr] | = temp <iproffset; // set the response priority and the disconnection priority.
}
// External Interrupt configuration function
// Only for gpioa ~ G; do not include the following:
// Parameter: gpiox: 0 ~ 6, representing gpioa ~ G; bitx: bit to be enabled; trim: trim mode, 1, bottom-up, 2, top-down, 3, triggered at any level
// This function can be configured with only one IO port and multiple I/O Ports at a time and needs to be called multiple times
// This function will automatically enable the corresponding interrupt and shield.
// Waiting for test...
Void ex_nvic_config (u8 gpiox, u8 bitx, u8 trim)
{
U8 extaddr;
U8 extoffset;
Extaddr = bitx/4; // obtain the number of the interrupt register group
Extoffset = (bitx % 4) * 4;
RCC-> apb2enr | = 0x01; // enable Io multiplexing of clock
Afio-> exticr [extaddr] & = ~ (0x000f <extoffset); // clear the original settings !!!
Afio-> exticr [extaddr] | = gpiox <extoffset; // exti. bitx ing to gpiox. bitx
// Automatically set
Exti-> IMR | = 1 <bitx; // enable line bitx interruption.
// Exti-> EMR | = 1 <bitx; // events on line bitx are not blocked (if this sentence is not blocked, it is acceptable on the hardware, but it cannot be interrupted during software simulation !)
If (TRIM & 0x01) exti-> ftsr | = 1 <bitx; // triggered by event descent along line on line bitx
If (TRIM & 0x02) exti-> rtsr | = 1 <bitx; // triggered when the event is raised along the upstream and downstream of line bitx
}
// You cannot reset all peripherals here! Otherwise, at least the serial port does not work.
// Reset all clock registers
// Check OK
// 091209
Void myrcc_deinit (void)
{
RCC-> apb1rstr = 0x00000000; // reset ended
RCC-> apb2rstr = 0x00000000;
RCC-> ahbenr = 0x00000014; // enables the flash memory and SRAM clock in sleep mode. Other functions are disabled.
RCC-> apb2enr = 0x00000000; // disable the peripheral clock.
RCC-> apb1enr = 0x00000000;
RCC-> Cr | = 0x00000001; // enables the Internal High-Speed clock hsion
RCC-> cfgr & = 0xf8ff0000; // reset SW [1:0], hpre [], ppre1 [], ppre2 [], adcpre [1:0], MCO []
RCC-> Cr & = 0xfef6ffff; // reset hseon, csson, pllon
RCC-> Cr & = 0 xfffbffff; // reset hsebyp
RCC-> cfgr & = 0xff80ffff; // reset pllsrc, pllxtpre, pllmul [] and usbpre
RCC-> CIR = 0x00000000; // close all interrupts
// Configure the vector table
# Ifdef vect_tab_ram
My_nvic_setvectortable (nvic_vecttab_ram, 0x0 );
# Else
My_nvic_setvectortable (nvic_vecttab_flash, 0x0 );
# Endif
}
// The thumb command does not support assembly inline.
// Execute the Assembly command WFI using the following method
// Check OK
// 091209
_ ASM void wfi_set (void)
{
WFI;
}
// Enter the standby mode
// Check OK
// 091202
Void sys_standby (void)
{
SCB-> SCR | = 1 <2; // enable sleepdeep (sys-> CTRL)
RCC-> apb1enr | = 1 <28; // enable the power clock
PWR-> CSR | = 1 <8; // set wkup to wake up
PWR-> Cr | = 1 <2; // clear the wake-up flag
PWR-> Cr | = 1 <1; // PDDs location
Wfi_set (); // run the WFI command
}
// Backup register write operation
// REG: Register ID
// REG: value to be written
/// Check OK
/// 091202
// Void bkp_write (u8 Reg, 2010dat)
//{
// RCC-> apb1enr | = 1 <28; // enable the power clock
// RCC-> apb1enr | = 1 <27; // enables backup of the clock
// PWR-> Cr | = 1 <8; // Cancel backup zone write Protection
// Switch (REG)
//{
// Case 1:
// Bkp-> DR1 = dat;
// Break;
// Case 2:
// Bkp-> DR2 = dat;
// Break;
// Case 3:
// Bkp-> dr3 = dat;
// Break;
// Case 4:
// Bkp-> DR4 = dat;
// Break;
// Case 5:
// Bkp-> DR5 = dat;
// Break;
// Case 6:
// Bkp-> dr6 = dat;
// Break;
// Case 7:
// Bkp-> dr7 = dat;
// Break;
// Case 8:
// Bkp-> dr8 = dat;
// Break;
// Case 9:
// Bkp-> dr9 = dat;
// Break;
// Case 10:
// Bkp-> dr10 = dat;
// Break;
//}
//}
// Soft system reset
// Check OK
// 091209
Void sys_soft_reset (void)
{
SCB-> aircr = 0x05fa0000 | (u32) 0x04;
}
// Set the JTAG mode. It is used to set the JTAG mode.
// Mode: JTAG, SWD mode setting; 00, full enable; 01, enable SWD; 10, disable all;
// Check OK
// 100818
Void jtag_set (u8 Mode)
{
U32 temp;
Temp = mode;
Temp <= 25;
RCC-> apb2enr | = 1 <0; // enable secondary clock
Afio-> mapr & = 0xf8ffffff; // clear mapr []
Afio-> mapr | = temp; // sets the JTAG mode.
}
// System clock initialization Function
// PLL: the number of multiplier selected. The value ranges from 2 to 16.
// Check OK
// 091209
Void stm32_clock_init (u8 PLL)
{
Unsigned char temp = 0;
Myrcc_deinit (); // reset and configure the vector table
RCC-> Cr | = 0x00010000; // hseon
While (! (RCC-> Cr> 17); // wait until the external clock is ready
RCC-> cfgr = 0x00000400; // apb1 = div2; apb2 = div1; AHB = div1;
PLL-= 2; // offset 2 units
RCC-> cfgr | = PLL <18; // set the PLL value to 2 ~ 16
RCC-> cfgr | = 1 <16; // pllsrc on
Flash-> ACR | = 0x32; // two flash delay periods
RCC> Cr | = 0x01000000; // pllon
While (! (RCC-> Cr> 25); // wait for the PLL to lock
RCC-> cfgr | = 0x00000002; // The PLL is used as the system clock.
While (temp! = 0x02) // wait until the PLL is successfully set as the system clock
{
Temp = RCC-> cfgr> 2;
Temp & = 0x03;
}
}
... \ .. \ System \ sys \ SYS. C (77): Error: #136: struct "<unnamed>" has no field "IPR"
