Nor flash operation

Title: norflash Learning
Tags: Arm
Date: 18:31:59
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Norflash: learning the difference between nor and NAND Flash

	Nor	Nand
Capacity	1 ~ 32 MB	16 ~ 512 MB
Xip executable program	Yes(Because it is a memory interface)Allows random access to data from any address.	No
Erased	Very slow (5S)	Fast (3 ms)
Write	Slow	Fast
Read	Fast	Fast
Reliability	Relatively high, the ratio of bit inversion is less than 10% of that of NAND Flash	Relatively low: Bit inversion is common and verification measures must be taken, such as "1-4 bit EDC/ECC" and bad block management measures.
Erasable times	10000 ~ 100000	100000 ~ 1000000
Lifecycle	Less than 10% of NAND Flash	10 times more than nor flash
Interface	AndRamSame interface	I/O interface
Access Method	Random Access	Sequential access
Ease of use	Easy	Complex
Main Purpose	It is often used to save code and key data.	Used to save data
Price	High	Low

• The block size range of nor flash is 64kb and 128kb: The block size range of NAND Flash is 8kb and 64kb. It takes 4 s to erase/Write A nor flash block, it takes only 2 ms to erase/Write a NAND Flash block.
• Generally, NAND Flash reads and writes data in 512 bytes. This makes nor flash suitable for running programs, while NAND Flash is more suitable for storing data.
• With the same capacity, NAND Flash is smaller. Nor flash is usually IMB ~ 4 MB (there are also 32 MB of nor flash), the capacity of NAND Flash is 8 Mb ~ 512 MB.
• Jffs2 file systems are often used in nor flash, while yaffs file systems are often used in NAND Flash. At the underlying layer, MTD drivers implement read, write, and erase operations on them, and it also implements EDC/ECC verification.
• Here, there are four banks in the nor used, and each bank has several blocks (erased size). The blocks in different banks may be different.

Pin Interface

For more information, see 2440 memory management.

Here, norflash is 16 bits, so the address line ignores A0.

Command

What does a command mean?

• Read MODEThat is, the address is sent first, and then data is obtained, which is the same as the normal READ memory.

• Reset Mode, Write to any address0xF0All exit special mode

• Read IDNor flash is divided into 1-byte and 2-byte modes, so there are two types of operation commands. The onboard is 2 bytes. The operation is as follows:
  1. Sending address 555, sending data AA, 0x555*2 = 0 xaaa
  2. Sending address 2AA, sending data 55 0x2aa * 2 = 0x554
  3. Sending address 555, sending data 90 0x555*2 = 0 xaaa
  4. Sending address 00, receiving data C2

However, the A1 of the on-board MCU is connected to A0 of nor, that is, the address x obtained by nor. The actual MCU needs to sendAddress x <1

Nor flash operations	2440 of operations	Actions on U-BOOT
Write AAH (unlock) to the address for 555h)	Write aah to the AAAH address (unlock)	MW. W AAA AA
Write 55 H (unlock) to address 2aah)	Write 55 H (unlock) to address 554h)	MW. W 554 55
Write 90 H (command) to address 555h)	Write 90 H to the AAAH address (command)	MW. w aaa 90
Read the address 0 to get the manufacturer ID (c2h)	Read the address 0 to get the manufacturer ID (c2h)	Md. w 0 1 (1: indicates read once)
Obtain the device ID (22dah or 225bh) from the read 1 address)	Obtain the device ID 2249 from the read 2 address.	Md. W 2 1 (1: indicates read once)
Exit read ID status: Write f0h to any address.	Exit read ID status: Write f0h to any address.	MW. w 0 F0

Note that this uboot should be started on nor, because norflash is invisible during NAND startup.

Device ID : MX29LV160DT: 22C4; MX29LV160DB: 2249.OpenJTAG> mw.w 0 f0OpenJTAG> mw.w aaa aaOpenJTAG> mw.w 554 55OpenJTAG> mw.w aaa 90OpenJTAG> md.w 0 100000000: 00c2    ..OpenJTAG> md.w 2 100000002: 2249    I"

Parameter Identification (CFI)

CFI (Common flash Interface) detection is to directly send various commands to read information about the chip, such as ID and capacity. The chip itself contains information such as the voltage and capacity. in fact, it is used first.55 address write 98And then read the parameters.

Generally, whether reading is supported firstCFI, That is

1. Write 98h to 55 h
2. Query0x10，0x11,0x12Is itQRYString
3. If yes, the CFI interface is supported.

Operate CFI on nor flash	2440 CFI operations	CFI operation on U-BOOT
Write 98 h to 55 h address	Write 98 h to Aah address	MW. w aa 98
The read address is 0051 in 10 h.	The read address is 0051 in 20 h.	Md. W 20 1
The read address is 0052 at 11 h.	Read address 22 h get 0052	Md. W 22 1
The read address is 0059 for 12 hours.	The read address is 0059 in 24 hours.	Md. W 24 1
The read address is 27h to get the capacity	Read address 4eh get capacity	Md. W 4E 1

Read address10, Read0x0051=‘Q‘Such as the size and address of the Read Device0x27, Will read0x15=2**15/1024/1024=2MFor specific parameters, refer to the standard documentation cfi100

Identifies the storage information. For specific information, search for the document cfi100.

We can see that there are four banks, reggion, and several other sector in region. this is the smallest unit of erasure. the calculation result is as follows. 2d is low and 2e is high. block = [2E: 2D] + 1,

	Blocks	Sector size
Bank1	1	256*0x0040/1024 = 16 K
Bank2	2	256x0x0020/1024 = 8 K
Bank3	1	256x0x0080/1024 = 32 K
Bank3	0x1e + 1 = 31	256*0x0100/1024 = 64 K
Total	35 blocks	Space size = 16 + 2*8 + 32 + 64*31 = 2048 K = 2 m

CFI description:

RemarksAnother figure in the manualTable 1-1. MX29LV160DT SECTOR ARCHITECTUREIt seems that the slice is in reverse order.

Write Data

Norflash is also a type of flash. data can be written only after data is erased. For erased units, commands are also required before data can be written.

Nor flash write operations	2440 write operation on	Write operations on U-BOOT
Write aah to address for 555h (unlock)	Write aah to the AAAH address (unlock)	MW. W AAA AA
Write 55 h to address 2aah (unlock)	Write 55 h to address 554h (unlock)	MW. W 554 55
Write a0h to address 555h	Write a0h to the AAAH address	MW. w aaa A0
Write PD to address Pa	Write 1234 h to address 0x100000	MW. W 100000 1234

Command reference, write to 1 m location, the address needs to be * 2, that is, 0x20, 0000

Openjtag> mW. w aaa aaopenjtag> mW. W 554 55 openjtag> mW. w aaa 80 openjtag> mW. w aaa aaopenjtag> mW. W 554 55 openjtag> mW. W 200000 30 openjtag> mW. w 0 f0openjtag> Md. W 200000 100200000: FFFF .. // read openjtag> mW. w aaa aaopenjtag> mW. W 554 55 openjtag> mW. w aaa a0openjtag> mW. W 200000 1234 openjtag> Md. W 200000 100200000: 1234 4. // you cannot directly write the code and need to execute the command openjtag> MW again. W 200004 5555 openjtag> Md. W 20000400200004: FFFF ..

Program Design

Note:The on-board load is a 16-bit width, and the address line is the A0 from the CPU A1 to the nor, so the MCU Address = The nor command address * 2.

Tools found during code debuggingMobaXterm_Personal_10.4Sometimes unable to accept serial port input, restart the software serial port

• Basic read/write operations

  # Define nor_base_bank 0/*** @ brief write Val * in the location based on nor mongo_addr. For example, write X in a 55 h location, that is, the address signal sends 55, * The actual address line is 55 <1 address line with the bank base address, * so the actual CPU address is base + (55 <1) * @ Param base * @ Param ADDR * @ Param Val */void norwriteu16 (uint16_t base, uint16_t ADDR, uint16_t Val) {volatile uint16_t * P = (volatile uint16_t *) (ADDR <1) + base); * P = val ;} /*** @ brief reads 2 bytes ** @ Param base * @ Param ADDR * @ Param Val */uint16_t norread2010( uint16_t base, uint16_t ADDR) {volatile uint16_t * P = (volatile uint16_t *) (ADDR <1) + base); return * P ;} /*** @ brief cmd write 16-Bit Data * @ Param ADDR cmd address * @ Param Val write value */void norflashcmdput (uint16_t ADDR, uint16_t Val) {norwriteu16 (nor_base_bank, ADDR, Val);}/*** @ brief cmd reads nor's 16-Bit Data ** @ Param ADDR * @ Param Val * @ return uint16_t */uint16_t norflash1_get (uint16_t ADDR) {return norread2010( nor_base_bank, ADDR );}

• Identify CFI

  Void norflashinfo (void) {// enter CFI mode, interface (CFI) mode norflashcmdput (0x55, 0x98); // start to read data uint8_t Buf [10] = {0, 0, 0, 0, 0, 0, 0}; // try to read "qry" Buf [0] = (uint8_t) norflash1_get (0x10); Buf [1] = (uint8_t) norflash1_get (0x11); Buf [2] = (uint8_t) norflash1_get (0x12); Buf [3] = (uint8_t) '\ 0 '; printf ("Get 0x20, 0x22,0x24 = % s \ r \ n", Buf); printf ("End \ r \ n"); norflashcmdput (0, 0xf0 );}

• Nor erasure and writing

  Note:Nor's physical address is the CPU address required>>1So the underlying functions are used before the address operation.CPU address> 1

  HoweverNor is 16-bit wide, that is, arranged as follows

  16-Bit Width	8-Bit Width
  00	00,01
  01	02,03
  02	04, 05
  03	06, 17

  We need to convert the 8-bit-width address to the 16-bit-width address, that is, ADDR> 1.

  Void do_write_nor_flash (void) {unsigned int ADDR; unsigned char STR [100]; int I, j; unsigned int val; /* obtain the address */printf ("Enter the address of sector to write:"); ADDR = get_uint (); printf ("Enter the string to write :"); gets (STR); printf ("writing... \ n \ r ");/* STR [0], STR [1] ==> 16bit * STR [2], STR [3] => 16bit */I = 0; j = 1; while (STR [I] & STR [J]) {val = STR [I] + (STR [J] <8);/* burn write */nor_cmd (0x555, 0xaa ); /* unlock */nor_cmd (0x2aa, 0x55); nor_cmd (0x555, 0xa0 ); /* Program * // This is the focus --------------------------------------------------- nor_cmd (ADDR> 1, Val); // This is the focus of attention/* Waiting for completion of writing: Read data, when Q6 is not changed, it indicates the end */wait_ready (ADDR); I + = 2; j + = 2; ADDR + = 2;} val = STR [I]; /* burn and write */nor_cmd (0x555, 0xaa);/* unlock */nor_cmd (0x2aa, 0x55); nor_cmd (0x555, 0xa0 ); /* Program */nor_cmd (ADDR> 1, Val);/* Wait for the data to be burned to finish: Read data. If Q6 is not changed, it indicates the end */wait_ready (ADDR );}

  FAQ:

  In the instructor's video, when the specific address of the nor is written, nor_cmd (ADDR> 1, Val); here the address shifts one to the right, the instructor explained that the address line A1-> A0. but I don't think so.
  Becausenor_cmdThe function has converted the address to the address of the nor perspective. That is to say, to write the X address in the nor, we should directly operate on the address X.

  But after the test, I found that the Code did run well? So where do I get it wrong?
  Later I thought that the nor is a 16-Bit Width, that is, the 0 in the nor actually corresponds to the storage unit [].

  Conclusion: The address> 1 here is not because of the address line offset (in fact, it is also because of the address line, because it is 16 bits, so the offset is 1 bits), but from the function perspective, the actual reason is that the nor address is 16 bits in width. We need to convert it to an ADDR with 8 bits in width> 1 to an address with 16 bits in width.

  The following tests write data to ADDR = 1.12Actually, it is written in and written into ADDR = 2.12Actually, it is written in 2, in ADDR = 3, and in 2.

  Reference

• Determine if it is busy (dq6)

  • Dq7: Data # polling bit, dq7 status changes during programming.
    Dq7 of the data read from the address being programmed in the programming process is the complement code to be written into the data. for example, if the written data is 0x0000 and the input dq7 is '0', the data read in the programming process is '1 '; when programming is complete, the data read is converted back to the input data, that is, '0 '. the dq7 output is '0' during the erasure process, and the output is '1' after the erasure is complete. Note that the read address must be an address within the erasure range.
    Ry/by #: High indicates 'stopped', and low indicates 'busy '.

  • Dq6: Rotation Position 1 (toggle bit 1 ).
    During programming and erasure, reading any address will lead to the rotation of dq6 (mutual transformation between 0 and 1). After the operation is complete, dq6 will stop the conversion.
    Dq2: Rotation Position 2 (toggle bit 2). When a sector is selected for erasure, read valid addresses (the addresses are within the range of the erased sectors) will rotate dq2.
    Note: dq2 can only determine whether a specific sector is selected and erased. however, it cannot be distinguished whether the disk is being erased or is being erased and paused. in contrast, dq6 can identify whether or not norflash is in the erased or erased state, but it cannot identify which one is selected quickly. therefore, the two locations are required to determine the slice and mode status information.

  • Dq5: exceeded timing limits. When the programmed or erased operation exceeds a specific internal Pulse Count, dq5 = 1; this indicates that the operation failed. changing '0' to '1' during programming results in dq5 = 1. '0' can be changed to '1' only after erasure '. when an error occurs, run the reset command (see Figure 1-1) to return to the read data status.

  • Dq3: (Sector erasure timing bit) sector erase timer, which only takes effect when the sector erasure command is executed. when the erased command is dq3 = 1, all input commands (except the erased pause command) are ignored. dq3 = 0. You can add additional sectors for multi-sector erasure.

    void wait_ready(unsigned int addr){    unsigned int val;    unsigned int pre;    pre = nor_dat(addr>>1);    val = nor_dat(addr>>1);    while ((val & (1<<6)) != (pre & (1<<6)))    {        pre = val;        val = nor_dat(addr>>1);         }}

Program Optimization

1. The instructor's write operation does not determine whether the address is a high or low address. That is, both the write 0 address and the write 1 address are written in two bytes of the 0 address, in fact, if you write 1, you should first read 0 and then 1. What will be involved in erasure? If both are erased first, there will be no such problem.

Other Design Points

1. Disable the interrupt when reading and writing norflash.

   This is because when we use nor to start the instance, when the CPU is interrupted, it will jump back to the 0 address, that is, reading the command from nor. If we operate nor at this time, obviously there is a problem with the address fetch, And it will crash. the previous serial port sometimes did not output a dead host. This may be the reason.

2. Nor is 16 bits in width, so the actual address needs>>1The actual address that nor should accept. For detailed analysis, see write operations in the program design section.

Nor flash operation