[Note]. How do I use watchdog_timer in niosii?

This article briefly describes how to use the watchdog_timer service and provides a simple example.

Environment: Altera Quartus 9.1 SP1 + niosii 9.1 software build tools for eclipse SP1

Step 1. Sample the interval timer core in the System Builder:

1. The interval timer core is named watchdog_timer in the example of the parameter in the system builder.

Figure 1 example of interval timer Core

2. Configure the interval timer Core

Figure 2 configure the interval timer Core

In the pre-setting of hardware options, select watchdog.

Note: The value set by timeout period is the overflow time value of the watchdog. The value is set to 1 S. Once the dog is enabled, the dog is not fed to the dog within 1 s, and the dog resets the processor.

Table 1 watchdog register options

Table 2 watchdog output signal options

Step 2 compile the CProgram

1. view the corresponding content in system. h.

# Define tuning interval # define interval 1 # define watchdog_timer_base 0x1002040 # define interval 32 # define interval 1 # define interval 12500u U # define interval 4 # define interval 0 # define interval 124999999ull # define when 1.0 # define watchdog_timer_name "/dev/watchdog_timer" # define when 1 # define when "S" # define when 1 # define when 0 # define watchdog_timer_span 32 # define when 1u # define when 0 # define watchdog_timer_type "altera_avalon_timer"
 

The input clock frequency of the 6th-line, niosii soft core, which is 125 MHz.

2. view the control register content in altera_avalon_timer_regs.h.

/* Control register */# define altera_avalon_timer_control_reg 1 # define partition (base) \__ io_calc_address_native (base, role) # define partition (base) \ Iord (base, role) # define iowr_altera_avalon_timer_control (base, data) \ IOWR (base, altera_avalon_timer_control_reg, data) # define partition (0x1) # define partition (0) # define partition (0x2) # define sequence (1) # define altera_avalon_timer_control_start_msk (0x4) # define sequence (2) # define altera_avalon_timer_control_stop_msk (0x8) # define sequence (3)
 

3. Demonstration procedure

# Include "system. H "# include" altera_avalon_timer_regs.h "// storage ing header file of the interval timer core # include" plugin "// storage ing header file of the PIO core # include" alt_types.h "# include # define q_led_on plugin (q_led_base, 1) # define q_led_off listener (q_led_base, 0)/** function: Initialize the watchdog * Note: Once the watchdog is initialized, it cannot be stopped again */# define init_wdt \ listener (watchdog_timer_base, \ Taobao)/** function: Dog feeding operation * usage: write any value to periodl and periodh */# define feed_wdt \ Taobao (watchdog_timer_base, 0x1234) int main (void) {alt_u8 I; init_wdt; // initialize the watchdog feed_wdt; // perform the dog feeding operation/** the LED must be highlighted for 10 times first */for (I = 0; I <10; I ++) {q_led_on; usleep (100*1000); feed_wdt; // q_led_off; usleep (100*1000); feed_wdt; // perform the dog feeding operation}/** the LED remains out for 2 s, and then re-open */q_led_off; usleep (500*1000); feed_wdt; // perform the dog feeding operation usleep (500*1000); feed_wdt; // perform the dog feeding operation usleep (500*1000); feed_wdt; // perform the dog feeding operation usleep (500*1000); feed_wdt; // perform the dog feeding operation q_led_on; while (1) {} return 0 ;}

Note: </unistd. h> is sent from a blog and does not belong to thisCode.

Line 14-16 initialize the watchdog, that is, start the watchdog. The specific operation is to give the start position 1 of the control register. Note: once started, the watchdog cannot be disabled again.

Line 21-22: Dog feeding. Whether you write any value for periodl or periodh, the watchdog will reset after the configured overflow time. The overflow time of the Watchdog in this article is 1 s, which is set when interval timer is configured in the FPGA builder. You can set it to another value. Therefore, in order to ensure that it is not reset, we need to feed the dog again within the overflow time after the dog is fed.

4. Running result

The LED flashes 10 times after being highlighted, 2 seconds after being turned on, and 1 second after being turned on.

Note that 2 seconds is due to the delay, while 1 second is due to the failure time of the guard dog to automatically reset; if there is no guard dog, the LED will remain on.

References

1. volume5: Embedded peripherals, quartuⅱ handbook version 9.1

Http://www.altera.com/literature/hb/nios2/n2cpu_nii5v3.pdf