[Note]. How to Use Debussy + Modelsim to quickly view the pre-simulation waveform

Introduction: Modelsim is a HDL simulation software, and Debussy is a waveform viewing software. The so-called quick view of the previous simulation waveform is only for reference. Do not stick to this. The functions of the two software are very powerful. Please study it on your own.

Note: The software environment in this blog post is Debussy 5.3v9 + Modelsim se 6.5.

Configuration

1. Install and harmony software. .

2. copy the file ..\ Novas \ Debussy \ share \ PLI \ modelsim_pli \ winnt \ novas. dllTo folder.. \ Modeltech_6.5 \ Win32.

3. Cancel a file.. \ Modeltech_6.5 \ ModelSim. iniOfRead-OnlyProperty.

Find

 
; Login User = Login User. SL
 

Replace

 
Export user = novas. dll
 

Save; close; set to read-only.

After the configuration is complete, it will be done once and for all.

Practice

Here is a simple divider. The file map is as follows:

 
│ RTL. f │ run. Bat │ Sim. Do │ restart-RTL clk_rst.v divider. V divider_tb.v
 

1. CompileHDL File: RTL levelCode+ Testbench code. Save in folderRTL.

(1) divider. V // RTL-level code Module

'Timescale 1ns/10 psmodule divider (input I _clk, input I _rst_n, output o_clk); parameter u_dly = 1; // log2 (5) = 2.3219 <= 3 Reg [] cnt_p; // rising edge count sub-// 5-digit rising edge counter: 0 ~ 4 // 4 = 5-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) cnt_p <= 0; else begin if (cnt_p = 4) cnt_p <= 0; else cnt_p <= # u_dly cnt_p + 1 'b1; endend // log2 (5) = 2.3219 <= 3 Reg [] cnt_n; // descent along the Count subscriber // 5-digit descent along the counter: 0 ~ 4 // 4 = 5-1 always @ (negedge I _clk, negedge I _rst_n) begin if (! I _rst_n) cnt_n <= 0; else begin if (cnt_n = 4) cnt_n <= 0; else cnt_n <= # u_dly cnt_n + 1 'b1; endend Reg o_clk_p; // output register of the rising edge clock // output the rising edge clock // 0 ~ 2 bytes-> 1 // (2 + 1 )~ 4 rows-> 0 // 2 = 5> 1 // 4 = 5-1 always @ (posedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk_p <= 0; else begin if (cnt_p <= 2) // 2 = 5> 1 o_clk_p <= 1; else o_clk_p <= 0; endend Reg o_clk_n; // drop the output register along the clock // drop the output along the clock // 0 ~ 2 bytes-> 1 // (2 + 1 )~ 4 rows-> 0 // 2 = 5> 1 // 4 = 5-1 always @ (negedge I _clk, negedge I _rst_n) begin if (! I _rst_n) o_clk_n <= 0; else begin if (cnt_n <= 2) // 2 = 5> 1 o_clk_n <= 1; else o_clk_n <= 0; endendassign o_clk = o_clk_n & o_clk_p; // bitwise AND (Role: mask) endmodule

(2) clk_rst.v // the clock and reset module of testbench

 
'Timescale 1ns/10 psmodule clk_rst (output Reg I _clk, output Reg I _rst_n); parameter clk_period = 20; parameter mult_ratio = 10; parameter reset_time = mult_ratio * clk_period + 1; initialbegin I _rst_n <= 1' B0; # reset_time I _rst_n <= 1 'b1; endinitialbegin I _clk <= 1 'b0; forever # (clk_period/2) I _clk <= ~ I _clk; endendmodule
 

Remove the clock and reset separately to facilitate transplantation to other platforms.

(3) divider_tb.v // test.pdf top-level sample module

 
'Timescale 1ns/10 psmodule divider_tb (); wire I _clk; wire I _rst_n; wire o_clk; // genrate clockclk_rst clk_rst_inst (. I _clk (I _clk ),. I _rst_n (I _rst_n); // user logicdivider divider_inst (. I _clk (I _clk ),. I _rst_n (I _rst_n ),. o_clk (o_clk); // dump fsdb file for debussyinitialbegin $ fsdbdumpfile ("wave. fsdb "); $ fsdbdumpvars; endendmodule
 

 

Note that rows 22nd to 27th

// Dump fsdb file for debussyinitialbegin $ fsdbdumpfile ("wave. fsdb"); $ fsdbdumpvars; End
 

This statement calls Modelsim to generate a waveform file and save it as wave. fsdb for Debussy to view.

2. WriteHDL file list fileFor Modelsim and Debussy.

RTL. f

 
RTL/divider. vrtl/clk_rst.vrtl/divider_tb.v
 

3. WriteModelSim command line script file.

Sim. Do

 
Vlib workvlog-f rtl. fvsim work. divider_tbrun 10usq
 

4. WriteBatch Processing STEP Files, Call the command line Modelsim to generate the waveform file, and then call debusyy to view it.

Run. bat

: Disable echo @ echo off: set the software path set Debussy = c: \ novas \ Debussy \ bin \ debussy.exe set vsim = c: \ modeltech_6.5 \ Win32 \ vsim.exe :: modelSim command % vsim %-C-do SIM. do: Delete the RD work/S/qdel transcript vsim file generated by ModelSim. wlf/Q: Debussy command % Debussy %-f rtl. f-SSF wave. fsdb-2001: Delete the waveform file del wave. fsdb/Q: delete the related file RD debussy.exe log/S/qdel Debussy generated by Debussy. RC/Q: exit the command line exit
 

Note: Modify the relevant path as needed. This document uses my personal configuration as an example.

5. Double-click Run. bat.

Display command line screen

Figure 1 run. bat

The Debussy and Debussy waveform viewing components are displayed.

Figure 2 Debussy and Debussy waveform viewing component

I call, where is the waveform. I am afraid that I can beat me.

Well, don't worry. Come on.

(6) Add the signal to be observed.

Click orSIgnal-GEt signals... Add a signal, or clickSIgnal-GetALl signals. Here I am just a little lazy, just add all the signals.

A warning is displayed, indicating that it takes some time to add all signals and whether to confirm them. OK.

Figure 3 warning

Look, the waveform is coming out.

Figure 4 simulation waveform before devider

Conclusion

As mentioned in the introduction, Modelsim is too powerful, so it is a little complicated. In the collaborative simulation with Debussy, we save a lot of unnecessary resources. Of course, there are many other functions. Due to the limited level, let's write them here.

Reference

1. Yuan qiuchun. Use Modelsim and Debussy to collaboratively simulate the process of using VHDL.

2 cmf3887299.debussy + Modelsim simulation process