[Note]. How to Use the interrupt of the nio ii: Pio interrupt and timer interrupt

ArticleDirectory

• 1 Pio interrupt
• 2. Timer interruption
• 2.2 C code for timer interruption
• 3 tips

Introduction

Timer interruption. I used to post in Amy's e-forum. I also discussed Pio interruption in my blog. Recently, I found a small mistake in my previous summary. So I wrote a blog post based on my recent experience in touch screen.

 

Software and hardware environment

Hardware: Amy ep2c8 core board + 2.4 'tft Kit

Software: Altera Quartus II 10.0 + NiO II 10.0 software build tools for eclipse

 

Content 1 Pio interrupted

Take the ads nirq pin as an example.

1.1 Pio sample in the System Builder

Figure 1.1 sample Pio Core

Figure 1.2 Basic Setting

Figure 1.3 input Option

In the ads7843, when the touch pen is used to touch the TFT, The nirq pin will be low, so we can detect the edge of the nirq pin and interrupt it when it is a descent edge. View the PIO section in the embedded peripherals IP user guide. According to the descriptions in Figure 1.4 and 1.5, set 1.3 For nirq Pio input options. You only need to configure the options shown in Figure 1.2 and Figure 1.3. Other options can be set by default.

Figure 1.4 capture functions

Figure 1.5 functions of IRQ generation

1.2 Pio interrupted C Code

# Include "system. H "// system # include" altera_avalon_pio_regs.h "// PIO, ads_nirq # include" sys/alt_irq.h "// interrupt // unsigned int nirq_isr_context; // define global variables to store the isr_context pointer void nirq_initial (void); void nirq_isr (void * isr_context); // int main (void) {nirq_initial (); // initialize Pio interrupt while (1) {}} // nirq interrupt initialize void nirq_initial (void) {// rewrite timer_isr_context pointer to match alt_irq_register () function prototype void * isr_context_ptr = (void *) & nirq_isr_context; interrupt (ads_nirq_base, 1); // enable interrupt terminate (ads_nirq_base, 1 ); // clear the interrupt edge capture register // register ISR alt_ic_isr_register (ads_nirq_irq_interrupt_controller_id, // The number of the interrupt controller, from system. h copy ads_nirq_irq, // hardware interrupt number, from system. h copy nirq_isr, // The interrupt service sub-function isr_context_ptr, // point to the data struct 0x0 related to the device driver instance); // flags, reserved unused} // interrupt service subfunction void nirq_isr (void * nirq_isr_context) {iowr_altera_avalon_pio_edge_cap (ads_nirq_base, 1); // clear interrupt edge capture register/User Interrupt code}

In this example, the 21st behavior enables the interrupt and clear interrupt edge capture registers to be operated by bit. Here the nirq pin is 1 bit, so the written value is 0 or 1.

 
Iowr_altera_avalon_pio_irq_mask (ads_nirq_base, 1); // enable interruption
 

If it is a bus, for example, four bits, then the following operations should be performed. Operations on other registers are similar.

 
Iowr_altera_avalon_pio_irq_mask (bus_4_base, 0xf); // enable interruption
 

At the same time, you must note that if enable bit-clearing for edge capture register is selected in the system builder, the edge capture should be a write 1 clearance interruption; if enable bit-clearing for edge capture register is not selected, it is an arbitrary number of cleaning interruptions. (Summarized by Han bin)

 
Iowr_altera_avalon_pio_edge_cap (ads_nirq_base, 1); // clear the interrupt edge capture register
 

If it is a bus, it is similar to the above.

In terms of definition interruption, We can summarize the following:For the arm and MIPS types, the Nios are 1-bit HD interrupt while 51 single-chip microcomputer is 0-bit HD interrupt.

Note:
1. Do not use printf () in the interrupted service code area. Otherwise, the interruption will be severely blocked.
2. If you need to interrupt the data transmission parameter of the Service subfunction, the parameter must be empty. The parameter is a 16-bit global variable.
3. There are two methods to describe interrupt registration after version 9.1. The example here is the interrupted registration method of enhanced version.

 

2. Timer interruption

Take high_res_timer as an example.

2.1 timer is optimized in the system of Image Processing Service (system) builder.

Figure 2.1 sample interval timer Core

Figure 2.2 configure timer counter size and hardware Option

View the interval timer kernel section in the embedded peripherals IP user guide. Refer to the descriptions in Figure 2.3 and 2.4 to configure a 32-bit full-featured timer (of course, you can also configure a 64-bit timer, but the software needs to be slightly modified later ). You only need to configure figure 2.2 and set other options by default.

Figure 2.3 counter size function

Figure 2.4 functions of hardware options

2.2 C code for timer interruption

# Include "system. H "// system # include" altera_avalon_timer_regs.h "// timer # include" sys/alt_irq.h "// interrupt // unsigned int timer_isr_context; // define global variables to store the isr_context pointer void timer_initial (void); void timer_isr (void * isr_context); // int main (void) {timer_initial (); // initialize timer interrupt while (1) {}} // timer interrupt initialize void timer_initial (void) {// rewrite timer_isr_context pointer to match alt_irq_register () function prototype void * isr_context_ptr = (void *) & tim Er_isr_context; // set the period register // periodh <16 | periodl = counter cycle factor * system clock frequency factor-1 // periodh <16 | periodl = 5 m * 100 m-1 = 499999 = 0x7a11f iowr_altera_avalon_timer_periodh (high_res_timer_base, 0x0007); iowr_altera_avalon_timer_periodl (high_res_timer_base, 0xa11f ); // set the control register // number of digits | 3 | 2 | 1 | 0 | // control | stop | START | cont | Ito | // Ito 1, resulting in IRO; 0, no IRQ is generated // cont 1. The counter runs continuously until stop is set to one.; 0, counting to 0 stop // start 1, the counter starts to run; 0, no impact // stop 1, the counter stops running; 0, no impact iowr_altera_avalon_timer_control (high_res_timer_base, altera_avalon_timer_control_start_msk | // start = 1 scheduled | // cont = 1 scheduled); // Ito = 1 // register the timer to interrupt alt_ic_isr_register (scheduled, // The number of the interrupt controller, from system. h copy high_res_timer_irq, // hardware interrupt number, from SY Stem. h copy timer_isr, // interrupt service sub-function isr_context_ptr, // point to the data struct 0x0 related to the device driver instance); // flags, reserved unused} // The subfunction void timer_isr (void * timer_isr_context) of the timer interrupt service {// returns the response interrupt and clears the Status Register iowr_altera_avalon_timer_status (high_res_timer_base ,~ Altera_avalon_timer_status_to_msk); // to = 0 // User Interrupt code}

Figure 2.3 32-bit register structure of the interval timer core.

View the interval timer kernel section in the embedded peripherals IP user guide. Refer to Figure 2.3 to set registers. Take 5 ms as an example. The system clock is 100 MHz. The reason for subtracting 1 is that the count starts from 0. For more information about the functions of other registers, see the related sections in the manual.

 
// Set the period register // periodh <16 | periodl = counter cycle factor * system clock frequency factor-1 // periodh <16 | periodl = 5 m * 100 m-1 = 499999 = 0x7a11f iowr_altera_avalon_timer_periodh (high_res_timer_base, 0x0007); iowr_altera_avalon_timer_periodl (high_res_timer_base, 0xa11f );
 

Similar to Pio considerations.
Note:
1. Do not use printf () in the interrupted service code area. Otherwise, the interruption will be severely blocked.
2. If you need to interrupt the data transmission parameter of the Service subfunction, the parameter must be empty. The parameter is a 16-bit global variable.
3. There are two methods to describe interrupt registration after version 9.1. The example here is the interrupted registration method of enhanced version.

3 tips

The interrupt operations of the niosii are similar. In the future, I will write how to use other IP addresses and user-defined IP address interruptions.

Embedded peripherals IP User Guide provides many IP core functions and usage instructions. It is a red treasure book to learn about niosii. For more details about the software programming of niosii, refer to the niosii software developer's Handbook. For more details about the niosii soft core, refer to the niosii processor reference handbook. If you have some problems that cannot be solved, you can go to alterafoum.com to search for related keywords. In many cases, you can find previous experiences and answers.

 

See also

[Note]. Differences between sys/alt_irq.h of niosii 9.1 and earlier versions. [niosii]

Reference

Altera. Embedded peripherals IP User Guide