Notes: Cyclone IV Chapter I FPGA device Series Overview

Because I use the four-generation development board of the black gold industry and the central chip uses the cycloneiv e of Altera, read the information on the device's official website and take notes for future reference.

The cyclone IV device family has the following features:
■ Low-cost, low-power FPGA Architecture:
■ 6 K to 150 K logical units
■ Up to 6.3 MB of Embedded Memory
■ Up to 18 × 18 multiplier for DSP processing-intensive applications
■ Protocol bridging application, achieving total power consumption of less than 1.5 W

Logical unit 15408

Embedded Memory 504 kbits

Embedded 18*18 multiplier 56

General PLL 4

Global clock network 20

User Io block 8

Maximum user I/O 343

 

 

FPGA Architecture

The architecture includes the Le, memory module, and multiplier composed of four input search tables (LUTs.

The m9k memory module of each cyclone IV device has 9 kbit Embedded SRAM memory.

The minimum depth that can be configured for each m9k is 512, and the maximum width is 18. Therefore, if the depth is less than 512, it will still occupy 1 block of RAM. If the width is greater than 18, an additional block of Ram will be occupied.

The embedded multiplier module can implement an 18 × 18 or two 9 × 9 multiplier in a single module.

The cyclone IV device I/O supports programmable bus persistence, programmable pull-up resistance, programmable latency, programmable drive capability, and programmable slew-rate control, thus realizing signal integrity and hot swapping optimization.

 

I/O standards supported by the cyclone IV Device Family

Type I/O standard
Single-ended I/O lvttl, lvcmos, SSTL, HSTL, PCI, and PCI-X
Differential I/O SSTL, HSTL, lvpecl, blvds, LVDS, mini-LVDS, RSDs, and ppds

 

The cyclone IV device consists of up to 30 gclk networks and up to 8 PLL (each with five outputs) to provide reliable clock management and integration.

Gclk is a global clock with dedicated cabling to the global clock network. The lhclk and rhclk in each part of the chip are regional clock, only the clock in some logical regions can be driven. In fact, the clock is designed for source synchronization and the speed is relatively fast. Generally, the global clock above MHz is designed for the main logic, which is relatively slow, below MHz, but only the global clock has link Delay Compensation

Altera provides the phy ip address, which can be used with your custom storage controller or the storage controller provided by Altera. The cyclone IV device supports Error Correction Code (ECC) bits on the DDR and DDR2 SDRAM interfaces.

 

Notes: Cyclone IV Chapter 1 FPGA device Series Overview