Notes on implementing the AES algorithm on FPGA

For AEs whose key length is 128 bitsAlgorithm.

1. the AES algorithm requires 10 rounds of operations. The most basic implementation is 11 cycles.

2. 16 sboxes are used for each round of encryption, and each sbox occupies 1 2048-bit Rom. Key expansion uses four sboxes. If on-the-fly is performed, a total of 20 sboxes are required. If the key expansion is prepared in advance, 16 sboxes and 1408 bits RAM are required to store the subkey.

3. on Altera FPGA, each sbox occupies one ESB or EAB. on Xilinx FPGA, each sbox occupies one block ram (because each block ram is dual-port ). In theory, AES encryption can be implemented using a piece of Spartan-II xc2100 (10 block RAMs) or a piece of flex epf10k200s (24 eabs.

4. in order to implement it on a cheap chip such as acex 1k30 (6 eabs), we need to break down one round into four steps. In this way, we only use four sboxes, together with the subkey, and use five eabs in total. Of course, 41 cycles is required to complete a 128-bit block encryption, and the throughput also drops to 1/4.