Half-life: data is sent
Not familiar: It is not understandable. I just used a few simple things.
Configuration DMA The procedure is as follows:
1. Turn on the clock.
Rcc_ahb1periphclockcmd (rcc_ahb1periph_dma2, enable );
2. Configure the DMA data structure
There are several clear points: Pass Usart 1 to send data, St F4 reference manual can be found in the usart1 said the corresponding channel: DMA2-Channel4-Stream7.
The data transmission direction is memory2peripheral. Memory to peripherals.
Do not use FIFO. The data to be transmitted is located in the usart_tx_buf [20] array. The usart1 data sending Register address is usart1_base + 0x04. The word width of the memory and peripherals is 1 byte.
For a single transmission, manual restart is required after the transmission is completed. The peripheral address is fixed and the memory address is automatically increased.
So:
Dma_deinit (dma2_stream7 );
Rcc_ahb1periphclockcmd (rcc_ahb1periph_dma2, enable );
Dma_structinit (& dma_initstructure );
Primary = dma_priority_medium;
Primary = dma_mode_normal;
Primary = dma_channel_4;
Primary = primary;
Primary = dma_primary omode_disable;
Signature = (uint32_t) usart_tx_buf;
Signature = usart1_base + 0x04;
Signature = bufsize;
Signature = dma_peripheraldatasize_byte;
region = dma_peripheraldatasize_byte;
region = dma_peripheralinc_disable;
dma_initstructure.dma_memoryinc = dma_memoryinc_enable;
then, use dma_init to initialize the DMA. Finally, dma_cmd is used to enable DMA.
dma_cmd is used to enable one DMA Operation each time data is sent. I have no other solutions .....
call in function:
while (1)
{< br> while (reset = usart_getflagstatus (usart1, usart_flag_txe);
usart_senddata (usart1, 'B');
while (reset = usart_getflagstatus (usart1, usart_flag_txe);
usart_senddata (usart1, 'A ');
delay_ms (1000);
printf ("argjiarjfgio \ r \ n");
If (set = dma_getflagstatus (dma2_stream7, dma_flag_tcif7 ))
{< br> dma_clearflag (dma2_stream7, dma_flag_tcif7);
// dma_cmd (dma2_stream7, disable);
for (I = 0; I <20; I ++)
usart_tx_buf [I] = I + 51;
dma_cmd (dma2_stream7, enable );
}< BR >}
Technorati Tag: 127f4, DMA, usart