OHCI (i)-OHCI spec

OHCI Register

registers related to Port power control:

Hcrhdescriptor.nps      nopowerswitchiing
hcrhdescriptor.psm      powerswitchingmode
hcrhstatus.lps          Clearglobalpower
hcrhstatus.lpsc         setglobalpower
hcrhdescriptorb.ppcm    portpowercontrolmask
HCRHPORTSTATUS.LSDA     Clearportpower
Hcrhportstatus.pps      setportpower

Configuration diagram

registers related to remote wakeup:

HCCONTROL.RWC   remotewakeupconnected//support remote wakeup
hccontrol.rwe remotewakeupenable   // Enable remote wakeup by upstream resume signaling
hcrhstatus.drwe deviceremotewakeupenable//enables Connectstatuschange bit as a resume event

registers related to Suspend/resume/reset:

Hcrhportstatus[i]. PSS   setportsuspend      //suspend
hcrhportstatus[i]. Poci  clearsuspendstatus  //resume
hcrhportstatus[i].prs   setportreset        //reset

ED

Ed (Endpoint descriptor) contains information about the endpoint used by HC, including the endpoint address, transmission speed, maximum packet size, and so on, containing the TD link head pointer HEADP and the tail pointer Tailp used in the ED, and the nexted pointing to the next ed.

When the HC process Ed, first will look at the skip and halted bit, if any one is set, then HC will skip this Ed and then to deal with an Ed, if skip and halted are not set, will compare HEADP and Tailp, different words, HEADP Point TD will be processed, HEADP and tailp the same words, stating that Ed has no need to be processed TD, can handle the next ed.

Control is mainly controlled using the control register Hccontrol (PLE, IE, CLE, BLE) and the command status register Hccommandstatus (CLF, BLF).
Take control transmission as an example:
1. The appropriate ED and TD parameters need to be set before controlling the transmission
2. You need to set the control transfer hccontrolheaded register and the hccontrolcurrented register to start the transfer, and then set the controlling register to allow the control transfer list, control the status register to control the transfer list data need to transfer
hccontrolheaded
hccontrolcurrented
Hccontrol = 0x90; Set Allow processing control transfer list
Hccommandstatus = OHCI_HC_COMMAND_STATUS_CLF;
3. Determine whether the data transfer ends in the interrupt handler. TD

TD (Transport descriptor) is a data structure for system memory that is used by HC to define buffers that send and receive data from endpoints. TD is divided into general TD and isochronous Td,general TD for interrupt, control, bulk transfer endpoint, isochronous TD for synchronous transmission endpoint. Ed and TD

In general, one Ed per endpoint, such as control transfer, requires only one Ed, while bulk transfer requires 2 Ed, respectively, for bulk out endpoint and bulk in endpoint.
Control transfer The ED below there are 3 TD, respectively, Setup, data, STATUS (for no DATA phase of the command, do not need the corresponding TD)
Bulk write out Ed below there are 2 TD, respectively is CBW, data,in ed below has a TD,CSW
Bulk read out Ed below there are 1 TD, respectively Cbw,in ED below there are two td,data, CSW

HCD is responsible for Ed's list node additions and linked list node deletions
HCD is responsible for TD link List node addition, under normal circumstances, the HC is responsible for TD linked List node deletion, but if the transmission error or from the customer software cancellation, the HCD is responsible for TD linked List node deleted.
When HC deletes the TD linked List node, the TD is first removed from the to-do queue and then added to the done queue.
Description: The done queue can be obtained from the Hcca Hccadonehead, while the to-do queue is actually the HEADP and Tailp point of the list in the ED, each time to add TD to Ed is to use the post-interpolation method, that is, add TD to the tail, and update Tailp. Hcca

The HCCA (Host Controller Communication area) is a 256-byte aligned memory data structure, and typically the interaction with HC can be done by reading the value of the HCCA structure or by writing to the HC Operation register. The system software sets the HCCA address to HC via the HCHCCA register.

Hcca. Hccadonehead and Hcdonehead
Hcdonehead Register contains the physical address of the last completed Transfer descriptor t Hat was added to the Do queue. When the HC reaches the end of a frame and its differed interrupt register is 0, it'll do:
1) When TD completed, HC Writes Hcdonehead to the NEXTTD field of TD
2) HC overwrites hcdonehead with the address of this TD
3) HC Write S hcdonehead to Hcca. Hccadonehead and then set Hcdonehead to zero, it alsa set WDH of Hcinterruptstatus.
4) Hcca. Hccadonehead is isn't written by the HC again until HCD clear WDH bit in Hcinterruptstatus reference article based on OHCI USB host s3c2440 USB Host Driver protocol based on OHCI protocol introduction