On-Chip Bus Wishbone Learning (5) Bus Cycle reset operation

On-Chip Bus Wishbone Learning (5) Bus Cycle-Overview of Reset operation Bus Cycle

A bus cycle consists of multiple clock cycles that cannot be divided, completing a single read/write operation, block read/write operation, or read rewrite operation. The bus cycle is also divided into a single read/write cycle, block read/write cycle, and read/write rewrite cycle. Data read/write operations are performed multiple times in a block read/write bus cycle. Generally, an operation is composed of a handshake between the master device and the control signal of the slave device, and a simultaneous transmission of the address and data bus. A block operation means that the entire operation needs to complete multiple data transfers. In the bus cycle, the master and slave devices are pre-configured to comply with the control signal handshake rules, and the transmission rules of the address and data bus are called Bus protocols.

In subsequent articles, the signals given in the example are the input and output signals of the master device. Therefore, the description of the operation is also from the perspective of the main device signal, so that you can understand the legend in the text. For example, "before the clock rising edge 1 reaches, the device detects the operation initiated by the master device and places the appropriate data to the input signals dat_ I () and tgd_ I () of the master device (), set the ack_ I height of the master device as the response to the stb_o of the master device. "The equivalent description is:" before the clock rising edge 1 reaches, the device detects the operation initiated by the master device and places the appropriate data to the output signal dat_o () and tgd_o (), set the output signal ack_o to a high value as a response to the stb_o of the master device. "

Reset operation

Resetting is the most basic operation of the digital system. After resetting, the system enters the predefined status. In systems that comply with Wishbone Bus Specifications, when the rst_ I signal is valid, the system begins to reset. Because the reset defined in the wishbone specification is a Synchronous Reset, after the reset signal is valid, all signals and registers enter the predefined state along the next clock rising edge. Therefore, the wishbone specification requires that the effective time of the rst_ I signal must be at least one clock cycle. In digital systems, Asynchronous Reset is usually used, and the length of the reset signal is generally greater than the system level stabilization time and system clock frequency stabilization time. If the wishbone interface uses Asynchronous Reset, it must be described in this document, because the wishbone interface uses Synchronous Reset by default.

Figure 1 reset operation of Wishbone Bus

For more information about synchronous and asynchronous resetting, see comparison between synchronous and asynchronous resetting.