On-Chip Bus Wishbone Learning (6) bus cycle operation initiation

On-Chip Bus Wishbone Learning (6) bus cycle operation initiation

A bus cycle consists of at least one bus operation. The operation is always initiated by the master device. The operation initiated by the master device can be a single read/write, block read/write, or rmw operation. When the master device sets cyc_o to high, a bus cycle begins. After the bus cycle starts, a bus operation starts when the master device sets stb_o to high. When the primary device sets cyc_o to low, all other signals of the primary device are meaningless. The operation initiated by the primary device is responded only when cyc_ I is high.

Cyc_o and stb_o can start from being invalid to being valid, and cyc_o continues to be valid until the operation ends. cyc_o and stb_o can start from being invalid to being valid at the same time to initiate a bus cycle at the same time, you can also initiate a bus operation, or change from valid to invalid, to indicate that the operation has ended. Therefore, when there is only one master device, cyc_o and stb_o can be combined into a signal. For example, this method is widely used in the source code of openrisc1200. The signal name is cycstb_o.

When multiple master devices exist, the cyc_o signal must be set to low in time after one master device completes the operation to allow the bus to be delivered to other master devices. In this case, the cyc_o signal is equivalent to the bus occupying the request signal.