One of the storage principles _ storage

Turn others, can not find the original source, feel the author. Storage principle:

In order to facilitate readers at different levels to understand the basic article, so I first to introduce a lot of users know things. The main function of RAM is to store code and data for the CPU to call when needed. But the data is not as simple as a bag of rice, but more like a library with a Plaid bookshelf to store books, not only to put in and to be able to make accurate calls when needed, although it is a book but each book is different. The same is true for memory such as RAM, although the code that represents 0 and 1 is stored, but different combinations are different data.

Let's go back to the books and shelves, if there is a bookshelf with 10 rows and 10 columns (each row and each column has 0-9 numbers), and 100 books to keep in it, then we can determine the position of a book by using a line number + a column number. If you know the number 87 of this book, we first lock the 8th line and find the 7th column to find the book exactly. Similar principles are used in RAM memory.

Now let's go back to ram memory, where the data bus is used for incoming or outgoing data. Because the storage space in the memory is defined by a certain rule as the book bookshelf mentioned earlier, we can use this rule to store the data in the corresponding position on the memory, and the work of this kind of positioning depends on the address bus select、read to realize. For the CPU, RAM is like a long thin line with many spaces, each of which has a unique address corresponding to it. If the CPU wants to call the data from RAM, it first needs to send the address data to the address bus select、read to locate the data to be accessed, then wait for several clock cycles, the data bus will transfer to the CPU. The following diagram will help you understand the process well.

Storage principle

The small garden point in the image above represents the storage space in RAM, each of which has a unique address line attached to it. When the address decoder receives the address data sent by address bus select、read, it locates the data that the CPU wants to call based on the data, and then the data bus sends the information to the CPU.

In the example listed above, the CPU accesses one byte of data at a time in a row of data, but in the real world it is different, usually the CPU needs to call 32bit or 64bit of data each time (this is determined by the bit width of the data bus of the different computer systems). If the data bus is 64bit, the CPU will be able to access 8 bytes in a single time, because each time it accesses 1 bytes of data, the 64bit bus will not show any advantage, the efficiency of women work will be much lower.

From "line" to "Matrix"

If RAM is only a "line" to the CPU, it does not reflect the actual operation. Because if that's the case, there's a lot of practical difficulty in actually making a chip, especially when it comes to designing large-capacity RAM. Therefore, a better way to reduce costs is to keep the "spaces" of information stored in many rows--each "space" corresponding to a bit storage location. In this way, if you want to store 1024bits of data, you can do so by using the 32x32 matrix. Obviously, a 32x32 matrix is more compact than a 1024bit line device and easier to implement. Take a look at the picture below:

Knowing what the basic structure of RAM looks like, let's talk about what happens when the byte is stored: The diagram above shows only the simplest condition, when there is only one RAM chip on the memory strip. For the X86 processor, it emits an address encoding with 22-bit binary digits via address bus select、read-11 bits are row addresses and 11 are column addresses, which are separated by the RAM address interface. The line address decoder (Row decoder) will first determine the row address, and then the column address decoder (columns decoder) will determine the column address, thus determining the location of the unique storage data, and then the data will be passed through the RAM data interface to the data bus. Also, it should be noted that the matrix for storing information inside RAM is not a square, that is, the number of rows and columns is not the same-the number of rows is less than the number of columns. (We'll talk about it later in the process of talking about DRAM.)

The diagram above outlines roughly how a basic SRAM chip works. SRAM is the abbreviation for "Static RAM", which is named because it does not disappear when the data is deposited (unlike DRAM dynamic random memory, which must be refreshed in a certain amount of time to keep the data stored therein). An SRAM unit is usually composed of 4-6 transistors, and when the SRAM cell is given a state of 0 or 1, it retains that state until the next time it is given a new state or the power is off before it changes or disappears. SRAM is relatively fast and saves power, but storing 1bit of information requires 4-6 transistors to make the cost too high (DRAM can be achieved with only 1 transistors).

RAM chips and SRAM chips

RAM Chip:

The previous introductions are relatively simple and abstract. Below we will introduce the actual RAM chip. When we talk about this issue, we will involve a more important technology: encapsulation. You should have heard of one or more of the terms of the 30-line Simms, 72-line Simms and 168-line DIMMs or RIMMs. If you want to explain the differences between these terms, you should understand the packaging technology of RAM.

SRAM Chip:

Early SRAM chips used 20-line dual-row (dip:dual Inline Package) encapsulation technology, they have so many pins because they have to: each address signal requires a signal line; a data input line and a data output line part of the control line (Write Enable, Chip Select); line and power cable

The image above shows the SRAM chip, but not the SRAM chip in the schematic below, the following is a 16K x 1-bit SRAM chip stitch function diagram:

A0-A13 is the address input signal pin, CS is the chip selection pin. In a real system, there must be a lot of chip SRAM, so you need to choose from that SRAM chip to write or read data. We are writing enabled pins (such as the table above, in CS, we above the line I did not write, indicating that the low level is valid or logic 0 o'clock valid): When the SRAM gets an address, it needs to know what to do, whether to write or read, we tell the SRAM to write the data. VCC is a power supply pin. DIN is the data input pin. Dout is the output pin of the data. GND is the grounding pin.

Output:

Enable (OE): Some SRAM chips also have this pin, but the image above does not. This pin is relative to the function of our pin, which allows SRAM to know what to read rather than write. Reading 1bit data from the Dout pins requires the following steps:
SRAM read operation: 1 by address bus select、read The address of the bit to be read to the corresponding read address pin (this time the/we pin should not be activated, so SRAM know that it should not do write operations). 2 Activate/cs to select the SRAM chip. 3 Activate/oe pin let SRAM know is read operation. After the third step, the data to be read is transferred from the dout pin to the bus. How is the process very simple? Similarly, the process of writing 1bit data is also very simple. SRAM Write operation: 1 determine where to write the information by address bus select、read (make sure the/oe pin is not activated). 2 The data bus will write to the dout pin. 3 Activate/cs PIN to select SRAM chip. 4 Activate the/WE PIN notification SRAM know to write operation.

After the four steps above, the data that needs to be written is placed where it needs to be written.

DRAM Chip Introduction

Now that we know the steps to read and write in a simple SRAM chip, let's take a look at how the average DRAM chip works. DRAM is more complex than SRAM because it requires constant refresh of stored information in the process of storing data in DRAM, which is the biggest difference between them. Let's look at the effect of the pins on the DRAM chip.

The earliest, simplest and most important DRAM chip was Intel's 2188 release in 1979, which is the 16kx1 DRAM 18-line dip package. The partial meaning of "16K x 1" tells us that this chip can store 16,384 bit data, at the same time can be 1bit read or write operations. I'm sorry I couldn't find the real picture of this chip, so I had to draw a simple sketch of it myself.

The diagram above shows that there is a distinct difference between DRAM and SRAM. First you'll see that the address pin changes from 14 to 7, so how does this 16K dram work with 16K SRAM? The answer is simple, DRAM divides the address into two consecutive clock cycles using a DRAM interface to transmit address data. This achieves the purpose of using half of the pins to achieve the same function as Sgram, which is known as multiplexing (multiplexing).

So why reduce the address pin it. What is the benefit of doing so? As we've described before, storing 1bit of data SRAM requires 4-6 transistors but DRAM only needs 1 transistors, so the same volume of SRAM is at least 4 times times larger than DRAM. This means that you do not have enough space to place the same number of pins (because the pins are not reduced by 4 times times). Of course, in order to install the same number of pins, can also increase the size of the chip, but this increases the chip production costs and power consumption, so reduce the number of pins is also necessary for the current large-capacity DRAM chip, multi-channel addressing technology is already essential.

Of course, the multi-channel addressing technology also makes the process of reading and writing more complex, so that when the design is not only the DRAM chip more complex, the DRAM interface is more complex, before we introduce the DRAM read and write process, please look at a DRAM chip internal structure diagram:

In the diagram above, you can see that there are two more parts of the DRAM structure than the SRAM: by/ras (Row address
Strobe: Line address pulse selector) pin-controlled row address latch line (row addressing Latch) and column address latch line controlled by/cas (column address strobe: The pulse selector of the row addresses) pin Latch). DRAM Read process: 1 The line address is transmitted to the address pin via address bus select、read. 2 the/ras pin is activated so that the line address is transmitted to the line address latch line. 3 The line address decoder selects the appropriate rows based on the data received.

4 The/we pin is determined not to be activated, so DRAM knows that it will not write. 5 The column address is transmitted via address bus select、read to the address pin. 6 The/cas pin is activated so that the column address is transmitted to the line address latch line. 7/cas Pin also has the function of/oe pin, so this time dout pin know the need to output data outward.

8/ras and/cas are not activated so that the next cycle of data operations can be performed. In fact, the writing process of DRAM and the reading process is basically the same, so if you really understand the above process can know the writing process, so here I do not repeat. (Just change the 4th step to/we the PIN is activated).

Basic knowledge of RAM

As we've already mentioned, the biggest difference between DRAM and SRAM is the inability to maintain data for a long time, a feature that makes this storage medium almost without any effect on us. But DRAM designers use the technology of refreshes to make DRAM known as the storage medium that is most useful to us now. Here I just briefly mention the DRAM refresh technique, because when we introduce the types of memory such as FP and Edo, you will find that they are different in their specific implementation process.

A dram can only hold the charge stored inside it for a very short time, so it needs to be refreshed before its charge disappears until the next time the data is written or the computer loses power. Each read and write operation refreshes the charge in the DRAM, so the DRAM is designed to read the contents of the DRAM regularly. There are several advantages to doing so. First, only use/ras to activate each row can achieve the goal of full refresh; second, the DRAM controller controls the refresh, which prevents the refresh operation from interfering with regular read and write operations. At the beginning of the article, I have said that the number of general rows is less than the column data. Now I can tell why this is the case, because fewer users will have less time to refresh.

RAM Module Basics:

In the previous section we made a few simple introductions to the basics of DRAM and SRAM, and in the examples we've listed are the most basic storage unit patterns, so it's not hard to understand, seeing a lot of friends who are interested in this stuff, Today I'll continue to introduce some of the knowledge about RAM (Random Access Memory). Understanding this part of the knowledge is the basis for a better understanding of the actual work of all kinds of RAM.

Each basic storage unit in an SRAM or DRAM (that is, the storage unit described in the previous section for storing 1bit of information) can store only 0 or 1 of such data, and in the previous section IDT6167 and Intel 2188 chips are only DIN (data input) and dout (data output interface), while the CPU access to data is in bytes (that is, 8bit) to store, then how RAM to meet the requirements of the CPU.

First, to store 1 bytes (8 bit) of information, 8 1bit RAM Base storage units are stacked together, which means that 8 chips are given the same address. The following diagram will help you to get a better view of this (only 4 memory units are drawn in the illustration shown below).

Typically, the 8 1bit chips are connected to the PCB (printed circuit board) via address bus select、read and data bus, which is a 8bit RAM chip for the CPU and is no longer a stand-alone 8 1 bit chip. The address bus bit width shown in the above image is 22bit, so that the capacity of the enclosure that this address bus can control should be 222=4194304bit, that is 4MB capacity; the bit width of the data bus is 8bit, This is done in parallel with the dout of the 8 1bit basic storage units mentioned earlier--which can also meet the CPU requirements. (For this storage particle we call 4194304 x 8 modules or 4mx8, note that the "M" here is not "MByte" but "Mbit"). For example, we use a TI (German instrument Company) produced by the Tm4100gad8 Simms memory as an example to illustrate, because the structure of the memory is relatively simple, easy to understand. Tm4100gad8 is based on 4M x 8 module, capacity 4MB, with 30-line Simms package. If you see what I said before, you should know that this memory uses 4mx1 dram particles. The following data I found on the TI website (currently very few company's website also provides its own previous product data): constructs: 4194304x8. Working voltage: 5-v. 30-line Simms (single In-line Memory module:simm). 8 pieces of 4Mbit dram memory particles, plastic SOJS package. Long Refresh period MS (1024 cycles).

In the diagram above, the A0–A10 is the address input pin. /cas: Line address pulse selector pin. DQ1–DQ8: Data input/Data output pins. NC: null signal pins. /ras: Column address pulse selector pin. VSS: Grounding pins. /w: Write-enabled pins. VCC 5V Power pins.

The schematic diagram above should give us a clearer understanding of the problem, Tm4100gad8 consists of 8 pieces of 4096x1bit chips, VCC and VSS provide 5v voltage for all chips. Each chip has a/ras,/cas,/w pin connected to the corresponding pin in memory. Each chip has a different data output/output interface. This way we should be able to know how RAM meets the CPU's need to access data.