One lesson per day (11/75) 80 × 86 memory management for CPU resources and memory

Memory Management Mode
Intel's 80x86 series CPU manages memory segments.

1. Memory segments
The memory management unit of a computer is linear addressing in bytes,Byte is the basic unit for memory management by 80 x86cpu. To identify each storage unit, a number is assigned to each storage unit, which is the physical address of the memory unit.
The physical address of a storage unit is a 16-bit binary number. The physical address is usually written in hexadecimal notation.

The 16-bit CPU has 20 internal address lines, and its addressing range is the power of 2, that is, 1 MB of memory space.
But the 16-bit CPU Memory Unit offset registers (IP, SP, BP, Si, Di, BX) encoding range is only: 00000 H-0 ffffh, that is, you can only access 65536 storage units, 64 K.
To be able to access 1 MB of memory space, the CPU adopts the memory segment management mode and adds segment registers to the CPU.
The 16-bit CPU divides the memory space into several logical segments. The requirements for each logical segment are as follows:
1) The starting address (segment address) of the logical segment must be a multiple of 16, that is, the last four binary bits must all be 0.
2) the maximum capacity of the logical segment is 64 KB, which is determined by the addressing space of the 16-bit register.

2. physical address Formation
Because the segment address must be a multiple of 16, the value is usually in the form of xxxx0h, that is, the first 16 bits are changed, and the last four bits are fixed 0, in view of this feature, you canOnly the first 16 binary bits are saved to save the entire segment address.Therefore, we need to remove four zeros (multiplied by 16) to the left of the segment register to obtain the actual segment address.
After determining the memory segment to which a storage unit belongs, we only know the scope of the storage unit (segment address to segment address + 65536 ), if you want to determine the specific location of the memory unit, you must also know how far the unit is from the segment address. We usually call the range between the actual address and the segment address of the storage unitIntra-segment offset, Also known as a valid address(Ef-effective address)OrOffset)With the segment address and offset, You can uniquely determine the specific location of a memory unit in the memory.

The logical address of a storage unit is divided into two segments: Offset
The formula for obtaining the physical address (Pa-physical address) from the logical address is: Pa = segment register value * 16 + offset (Why multiply by 16, because the segment register does not store the last four digits of the segment address, it must be * 16 or 4 digits left ).
In actual calculation, the PA = segment register <4 + offset is used. Because the left-shift operation is faster than the multiplication operation.

3. segment register reference
Segment registers are added to manage memory segments. The 16-bit CPU has four segment registers (and the 1 MB memory can be divided into 16 segments that do not overlap with each other ).ProgramYou can access four segments with different meanings at the same time.
1) Cs + IPCodeSegment access points to the memory segment used to store the program, and the Register IP points to the offset of the next command to be executed in the CS segment. With these two registers, you can obtain a physical memory address, this address stores a command to be executed: CS <4 + IP.
2) access to the SS + bp/SS + SP stack segment directs to the memory segment used to store the stack, and SP always points to the top of the stack, you can directly access the physical memory location of the top unit of the stack through the SS and SP registers. In addition, when the offset uses the pointer register BP, the default segment register is also ss, in addition, you can use BP to access the entire stack, not just the top data of the stack. (This is a way to directly operate the stack segment without using the stack's elastic stack mechanism)
3) access to the DS + bx data segment. The value in DS is shifted four places to get the starting address of the additional segment, and the offset in BX is added to get the physical address of a storage unit.
4) access to the additional elasticsearch + bx segment. The value of elasticsearch shifts left to get the starting address of the additional segment, and the offset in the Bx to get the physical address of a storage unit.

Reference relationship between segment registers and pointer registers:

Access storage		Default segment register	Optional segment registers	Offset
Command		CS		IP
Stack operations		SS		SP
Returns the operand.		DS	CS, es, SS	Valid address
String operation	Source operand	DS	CS, es, SS	Si
	Target operand	Es		Di
Use Pointer register BP		SS	CS, DS, es	Valid address

The 16-bit CPU has the following Conventions on the reference of segment registers:
1). The segment registers and offsets used for obtaining commands must use CS and IP addresses.
2). Used by stack operationsThe segment registers and offsets must use SS and SP
3). The registers and offsets used by the destination operand of the string operation must be es and Di.
4) In other cases, besides the default referenced registers, the segment registers can also be forcibly changed to other segment registers.

4. Contents of the storage unit

The above three chapters show us how to calculate the physical address of memory units, so that we can easily specify the storage units we want to access, but we also need to know how the content of the storage unit is stored.
The binary information stored by a storage unit is usually called the content or value of the storage unit:
1) the content of a byte is the binary information stored in the memory of the byte unit.
2) The content of a word is the Unit pointed to by the word address and the content of a subsequent unit.
3) The content of a dual-word address is composed of the units pointed to by the address and the content of the subsequent three units.

When splicing a cell, we follow the principle of high, high, low, and low. That is, the value of a high storage unit (a storage unit with a large address) is the 8-bit higher than the value of "Word content, the value of a low storage unit (a storage unit with a small address) is the 8-bit lower of the word content.

5. 32-bit microcomputer Memory Management Mode
The 32-bit PC memory management still adopts the "segment" management mode. The logical address of the memory is also composed of the segment address and offset, the memory management of a 32-bit PC differs from that of a 16-bit PC, because a 32-bit PC uses two different ways of working: real-time mode and protection mode.
(1) Calculation of physical addresses
1) In real mode
In real mode, the lower part of the address is still a multiple of 16, the maximum capacity of each segment is still 64 K, and the segment register value * 16 is the starting address, the physical address of the storage unit is still the segment address + intra-segment offset. In actual mode, the memory management of the 32-bit microcomputer is consistent with that of the 16-bit microcomputer.
2) protection mode
The segment address can be up to 32 bits, and its value can no longer be a multiple of 16. The maximum capacity of each segment can reach 4 GB, the value of the segment register is the "selector" that represents the segment address. With this "selector", a 32-bit segment address can be obtained from the memory, the physical address of the storage unit is the offset in the segment added to the segment address, which is completely different from the physical address calculation method of the 16-bit microcomputer.
(2) segment register reference
The 32-bit CPU has 6 segment registers, and the program can access 6 different segments at a specific time. The CIDR Block Value has different meanings in different methods:
1) in the real mode, the value of the lower register * 16 is the segment address.
2) In the protection mode, the value of the lower segment register is a selector that indirectly points out a 32-bit segment address.

Code segment register: When a 32-bit PC obtains the command, the system automatically references CS and EIP to obtain the next command. In actual mode, the maximum capacity of the segment cannot exceed 64 KB, therefore, the 16-bit EIP height is 0, that is, the EIP and the IP address are the same in real mode.

Stack segment register: When a 32-bit PC accesses a stack segment, it always references the stack segment register ss. However, stack pointers vary in different ways:
1) In actual mode, 32-bit PC uses the low 16-bit SP of ESP as the pointer to the stack. Therefore, we can think that the top unit of the stack is specified by the SS and SP registers, the method is the same as that for accessing the top unit of the stack in 16-bit PC mode.
2) In the protection mode, the stack pointer can use 32-bit ESP and 16-bit sp

data segment register: DS is the main data segment register. Generally, DS is the main register used to access data outside the stack. In some string operations, the segment register of the destination operand is specified as es, which is an exception.
the other register CS, SS, es, FS, and GS can also be used as the registers when accessing data. However, they must be written directly in the instruction in the way that segments exceed the prefix, in this way, the length of the instruction is increased, and the execution time of the instruction is also extended.
generally, data segments frequently used by programs are pointed to by DS. data segments that are not commonly used can be pointed to by ES, FS, and Gs.
(3) Contents of the storage unit
the storage format of the 32-bit microcomputer storage unit is exactly the same as that of the 16-bit microcomputer, we also use the "high, low, and low" principle to store data.