One lesson per day (9/75) the main role of CPU resources and memory General registers

Functions of General registers

In short, segment registers (ES, Cs, SS, DS, FS, GS) and address change registers (Si, DI) are used together to access segment data, the pointer register (BP, SP) is used to operate the stack. BP points to the base address of the stack, and SP always points to the top of the stack.

In addition, the command pointer EIP stores the next command to be executed inCodeThe offset in the segment. In the actual mode, the maximum range of each segment is 64 K, so the 16-bit height of the EIP is 0.

Register Classification		Register	Main use path
Connect Use Send Storage Tool	Data Register	Ax	Multiplication and division operations, input and output of words, and cache of intermediate results
		Al	Multiplication and division of bytes, input and output of bytes, and decimal arithmetic operation
		Ah	Byte multiplication and division operations to store interrupted function numbers
		BX	Memory pointer
		CX	Counter for string operation and loop control
		Cl	Shift operation counter
		DX	Multiplication, division, and indirect input and output of words
	Address Change Register	Si	Memory pointer, source operand pointer in string instruction
		Di	Destination operand pointer in memory pointer and string instruction
	Address Change Register	BP	Memory pointer and access Stack pointer
		SP	Stack top pointer
Command pointer		IP/EIP
Flag register		Flag/eflag
32-bit CPU Segment register	16-bit CPU Segment register	Es	Additional segment register
		CS	Code segment register
		SS	Stack segment register
		DS	Data Segment register
	Newly Added Segment register	FS	Additional segment register
		GS	Additional segment register

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1. Data Register

Data registers are mainly used to save information such as the operands and operation results, thus saving the time required to read the operands by occupying the bus and accessing the memory.

The 32-bit CPU has four 32-bit General registers eax, EBX, ECx, and EDX. Access to low 16-bit data does not affect high 16-bit data. These 16-bit low registers are named ax, BX, CX, and DX respectively, which are consistent with the registers in the previous CPU.

4 16-bit registers can be divided into 8 independent 8-bit registers (ax: Ah-Al, Bx: bh-BL, CX: ch-cl, DX: DH-DL ), each register has its own name and can be accessed independently.ProgramThe staff can flexibly process the word/byte information by taking advantage of the "severable" feature of the data register.

	Registers ax and Al are usually called accumulator. Operations with accumulators may take less time. Accumulators can be used for multiplication, division, input/output, and other operations. They are frequently used;
	Register BX is called base register ). It can be used as a memory pointer;
	Register CX is called count register ). During loop and string operations, use it to control the number of loops. during in-place operations, use Cl to specify the number of shifts when multiple bits are moved;
	Register dx is called a data register ). During multiplication and division operations, it can be used as the default operand for calculation, or it can be used to store the port address of I/O.

In a 16-bit CPU, ax, BX, CX, and DX cannot be used as the base address and address change register to store the address of the storage unit, but in a 32-bit CPU, its 32-bit registers, eax, EBX, ECx, and EDX, can not only transmit data, temporarily store data to save Arithmetic Logic calculation results, but also serve as a pointer register, these 32-bit registers are more universal. For details, see section 3.8-32-bit address addressing.

2. Address Change register

The 32-bit CPU has two 32-bit General registers ESI and EDI. Its Low 16 bits correspond to the Si and Di in the previous CPU, and its access to low 16 bits of data does not affect the high 16 bits of data.

Registers ESI, EDI, Si, and Di are called index register, which are mainly used to store the offset of the storage unit in the segment, they can be used to address multiple types of memory operations (detailed in chapter 3rd) to facilitate access to storage units in different addresses.

The address change register cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.

They can be used as general memory pointers. In the execution of string operation commands, they have specific requirements and special features. For more information, see section 5.2.11.

3. pointer register

The 32-bit CPU has two 32-bit General registers, EBP and ESP. Its Low 16 bits correspond to the same memory and SP in the previous CPU, and its access to low 16 bits of data does not affect the high 16 bits of data.

Registers EBP, ESP, BP, and SP are known as pointer register and are mainly used to store the offset of the storage unit in the stack, they can be used to address multiple types of memory operations (detailed in chapter 3rd) to facilitate access to storage units in different addresses.

Pointer registers cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.

They are mainly used to access the storage units in the stack and stipulate that:
	BP is a base pointer register that can be used to directly access data in the stack;
	SP is the stack pointer register, which can only access the top of the stack.

4. segment register

Segment registers are set based on the management mode of memory segments. The physical address of a memory unit is composed of the block register value and an offset, so that two smaller-digit values can be combined into a memory address that can access a larger physical space.

& Lt; TD align = "right" width = "6%" & gt; & lt;/TD & gt; & Lt; TD align = "right" width = "6%" & gt; & lt;/TD & gt; & Lt; TD align = "right" width = "6%" & gt; & lt;/TD & gt; & Lt; TD align = "right" width = "6%" & gt; & lt;/TD & gt; & Lt; TD align = "right" width = "6%" & gt; & lt;/TD & gt; & Lt; TD align = "right" width = "6%" & gt; & lt;/TD & gt;

segment registers inside the CPU:

cs -- code segment register (code segment register); its value is the segment value of the code segment.

DS -- data segment register (data segment register); its value is the segment value of the data segment.

es -- extra segment register; its value is the segment value of the additional data segment.

SS -- stack segment register (stack segment register); its value is the segment value of the stack segment.

FS -- extra segment register; its value is the segment value of the additional data segment.

Gs -- extra segment register; its value is the segment value of the additional data segment.

In a 16-bit CPU system, there are only four segments of registers. Therefore, the program can directly access up to four segments in use at any time. In a 32-bit microcomputer system, it has six segment registers. Therefore, a program developed in this environment can access up to six segments at the same time.

The 32-bit CPU has two different ways of working: real-time mode and protection mode. In each mode, segment registers have different functions. The regulations are described as follows:

Implementation Method:	The first four segment registers CS, DS, es, and SS have exactly the same meaning as the segment registers corresponding to the previous CPU. The logical address of the memory unit is still "segment value: offset format. To access data in a memory segment, the offset between the register and the storage unit must be used.
Protection Method:	In this method, the situation is much more complicated. The block register is not a segment value, but a value called "selector. The specific functions of segment registers are not further described here. Interested readers can refer to other technical materials.

5. Instruction Pointer register

The 32-bit CPU extends the instruction pointer to 32-bit and records it as an EIP. The 16-bit low of the EIP works the same as the IP address in the previous CPU.

The EIP and instruction pointer are the offsets of the commands to be executed next time in the code segment. In a system with the prefetch command function, the command to be executed next time is usually prefetch into the command queue unless the transfer occurs. Therefore, the command queue is not considered when you understand their functions.

In actual mode, because the maximum range of each segment is 64 K, the 16-bit high in the EIP must be 0. At this time, it is equivalent to only using its low 16-bit IP address to reflect the execution order of commands in the program.