OpenRISC Introduction (9)-based on or1200 minimum SOPC system (iii)--serial port

I recently got OpenRISC, someone was working on it, and wrote a master thesis, I've uploaded:

http://download.csdn.net/detail/rill_zhen/5303401

The following content should be based on the guidance of the paper completed, but not my completion, so reproduced as follows:

Connect an article (original) based on or1200 minimum SOPC system (ii)--QUARTUII project and DE2 platform download Now add the serial port to the or1200 minimum system. Simulate first, then verify on DE2, and show Hello world! on HyperTerminal

From the opencores website download uart16550_latest.tar.gz, the OR1200_SOPC directory under the new uart16550 directory, the source of the uart16550 in the extract to this directory. Modify the or1200_sys.v file. The revised document reads as follows:

Module Or1200_sys (input clk_i, input rst_n,//Buttons input [15:0] SW, UART interface Input uart_rxd, output uart_txd,//Segments OU
    
     
    
Tput [31:0] ledr);
    
     
    
       Wire rst = ~rst_n;
    
       //Wires from OR1200 inst Master to Conmax M0
    
       Wire wire_iwb_ack_i;
    
       Wire wire_iwb_cyc_o;
    
       Wire wire_iwb_stb_o;
    
       Wire [31:0] wire_iwb_data_i;
    
       Wire [31:0] wire_iwb_data_o;
    
       Wire [31:0] wire_iwb_addr_o;
    
       Wire [3:0] wire_iwb_sel_o;
    
       Wire wire_iwb_we_o;
    
       Wire Wire_iwb_err_i;
    
          
    
       Wire wire_iwb_rty_i; //Wires from OR1200 Data Master to Conmax M1//************************************************** wire wire_dwb_ack_i;
    
       Wire wire_dwb_cyc_o;
    
       Wire wire_dwb_stb_o;
    
       Wire [31:0] wire_dwb_data_i;
    
       Wire [31:0] wire_dwb_data_o;
    
       Wire [31:0] wire_dwb_addr_o;
    
       Wire [3:0] wire_dwb_sel_o;
    
       Wire wire_dwb_we_o;
    
       Wire Wire_dwb_err_i;
    
          
    
       Wire wire_dwb_rty_i; //wires from Conmax s0 to ONCHIP_RAM0/* *
    
       Wire wire_ram0_ack_o;
    
       Wire wire_ram0_cyc_i;
    
       Wire wire_ram0_stb_i;
    
       Wire [31:0] wire_ram0_data_i;
    
       Wire [31:0] wire_ram0_data_o;
    
       Wire [31:0] Wire_ram0_addr_i;
    
       Wire [3:0] wire_ram0_sel_i;
    
     
    
       Wire wire_ram0_we_i; // *********************************************Wires from Conmax S1 to GPIO//**************************************************
    
       Wire wire_gpio_ack_o;
    
       Wire wire_gpio_cyc_i;
    
       Wire wire_gpio_stb_i;
    
       Wire [31:0] wire_gpio_data_i;
    
       Wire [31:0] wire_gpio_data_o;
    
       Wire [31:0] Wire_gpio_addr_i;
    
       Wire [3:0] wire_gpio_sel_i;
    
       Wire wire_gpio_we_i;
    
       Wire wire_gpio_err_o;
    
          
    
  Wire Wire_gpio_interrupt; //wires from Conmax S2 to uart16550/* * *
    
       Wire wire_uart_ack_o;
    
       Wire wire_uart_cyc_i;
    
       Wire wire_uart_stb_i;
    
       Wire [31:0] wire_uart_data_i;
    
       Wire [31:0] wire_uart_data_o;
    
       Wire [31:0] Wire_uart_addr_i;
    
       Wire [3:0] wire_uart_sel_i;
    
       Wire wire_uart_we_i; Wire WIre_uart_interrupt; Or1200_top u_or1200 (//System. Clk_i (Clk_i),. Rst_i (RST),. pic_ints_i ({B0,wire_uart_interr Upt,wire_gpio_interrupt}),. clmode_i (2 ' b00),//instruction Wishbone INTERFACE. Iwb_clk_i ( Clk_i),. Iwb_rst_i (RST),. Iwb_ack_i (Wire_iwb_ack_i),. Iwb_err_i (Wire_iwb_err_i),. Iwb_rty_i (WI
    
  re_iwb_rty_i),. Iwb_dat_i (Wire_iwb_data_i),. Iwb_cyc_o (Wire_iwb_cyc_o),. Iwb_adr_o (Wire_iwb_addr_o), . Iwb_stb_o (Wire_iwb_stb_o),. Iwb_we_o (Wire_iwb_we_o),. Iwb_sel_o (Wire_iwb_sel_o),. Iwb_dat_o (W ire_iwb_data_o), ' ifdef or1200_wb_cab iwb_cab_o (), ' endif//' ifdef OR1200_WB_B3//Iwb_cti_o ( 
    
  ),//Iwb_bte_o (),//' endif//Data wishbone INTERFACE. Dwb_clk_i (Clk_i),. Dwb_rst_i (RST),
    . Dwb_ack_i (Wire_dwb_ack_i),. Dwb_err_i (Wire_dwb_err_i),. Dwb_rty_i (Wire_dwb_rty_i),
  . Dwb_dat_i (Wire_dwb_data_i),. Dwb_cyc_o (Wire_dwb_cyc_o),. Dwb_adr_o (Wire_dwb_addr_o),. Dwb_stb_o (W
    
Ire_dwb_stb_o),. Dwb_we_o (Wire_dwb_we_o),. Dwb_sel_o (Wire_dwb_sel_o),. Dwb_dat_o (Wire_dwb_data_o), ' Ifdef or1200_wb_cab dwb_cab_o (), ' endif//' ifdef OR1200_WB_B3//Dwb_cti_o (),//Dwb_bte 
    
  _o (),//' endif//External Debug Interface. Dbg_stall_i (1 ' B0),. Dbg_ewt_i (1 ' b0), Dbg_lss_o (),. Dbg_is_o (),. Dbg_wp_o (),. Dbg_bp_o (),. Dbg_stb_i (1 ' B0),. Dbg_we_i (1 ' B0),. Dbg_adr_i (0),. Dbg_dat_i (0),. Dbg_dat_o (),. Dbg_ack_o (),//' ifdef OR1200 _bist///RAM BIST//Mbist_si_i (),//Mbist_so_o (),//Mbist_ctrl_i (),//' endif// Power Management. Pm_cpustall_i (0),. Pm_clksd_o (),. Pm_dc_gate_o (),. Pm_ic_gate_o (),. P
    
  M_dmmu_gate_o (),Pm_immu_gate_o (),. Pm_tt_gate_o (),. Pm_cpu_gate_o (),. Pm_wakeup_o (),. Pm_lvolt_o ());
    
  Wb_conmax_top U_WB (. Clk_i (Clk_i),. Rst_i (RST),//Master 0 Interface . M0_data_i (Wire_iwb_data_o),. M0_data_o (Wire_iwb_data_i),. M0_addr_i (Wire_iwb_addr_o),. M0_sel_i (WI
    
  Re_iwb_sel_o),. M0_we_i (Wire_iwb_we_o),. M0_cyc_i (Wire_iwb_cyc_o),. M0_stb_i (Wire_iwb_stb_o),
    
     
    
  . M0_ack_o (Wire_iwb_ack_i),. M0_err_o (Wire_iwb_err_i),. M0_rty_o (Wire_iwb_rty_i),//. M0_cab_i (), Master 1 Interface m1_data_i (wire_dwb_data_o),. M1_data_o (Wire_dwb_data_i),. m1_addr
    
  _i (Wire_dwb_addr_o),. M1_sel_i (Wire_dwb_sel_o),. M1_we_i (Wire_dwb_we_o),. M1_cyc_i (Wire_dwb_cyc_o), . M1_stb_i (Wire_dwb_stb_o),. M1_ack_o (Wire_dwb_ack_i),. M1_err_o (Wire_dwb_err_i),. M1_rty_o (Wire _dwb_rty_i),//. M0_cab_i (),//Slave 0 Interface. S0_data_i (Wire_ram0_data_o),. S0_data_o (Wire_ram0_data_i), . S0_addr_o (Wire_ram0_addr_i),. S0_sel_o (Wire_ram0_sel_i),. S0_we_o (Wire_ram0_we_i),. s0_cyc_o (Wire_ram0_cyc_i),. S0_stb_o (Wire_ram0_stb_i),. S0_ack_i (Wire_ram0_ack_o),. S0_err_i (0),. S0_r Ty_i (0),//.s0_cab_o (),//Slave 1 Interface. s1_data_i (Wire_gpio_data_o),. S1_data _o (Wire_gpio_data_i),. S1_addr_o (Wire_gpio_addr_i),. S1_sel_o (Wire_gpio_sel_i),. S1_we_o (Wire_gpio_we _i),. S1_cyc_o (Wire_gpio_cyc_i),. S1_stb_o (Wire_gpio_stb_i),. S1_ack_i (Wire_gpio_ack_o),. s1_e Rr_i (Wire_gpio_err_o),. S1_rty_i (0),//.s1_cab_o (),//Slave 2 Interface. s2_data_i (Wire_uart_data_o),. S2_data_o (Wire_uart_data_i),. S2_addr_o (Wire_uart_addr_i),. S2_sel_o (wire_uart_s el_i),. S2_we_o (Wire_uart_we_i),. S2_cyc_o (Wire_uart_cyc_i),. S2_stb_o (Wire_uart_stb_i),. S2_ack_i (Wire_uart_ack_o),
    
     
    
S2_err_i (0),. S2_rty_i (0)//,//.s0_cab_o (),);
    
    Ram0_top u_ram0 (. Clk_i (Clk_i),. Rst_i (RST),. Wb_stb_i (Wire_ram0_stb_i), . Wb_cyc_i (Wire_ram0_cyc_i),. Wb_ack_o (Wire_ram0_ack_o),. Wb_addr_i (Wire_ram0_addr_i),. wb_sel_i (Wire_ram0_sel_i),. Wb_we_i (Wire_ram0_we_i),. Wb_data_i (Wire_ram0_data_i),. Wb_data_o (Wire_ram0
    
     
    
_data_o)); Gpio_top U_gpio (//Wishbone Interface. Wb_clk_i (Clk_i),. Wb_rst_i (RST),. Wb_cyc_i (Wire_gpio_cyc_i),. Wb_adr_i (Wire_gpio_addr_i),. Wb_dat_i (Wire_gpio_data_i),. Wb_sel_i (Wire_gpio_sel_i),. Wb_we_i (Wire_gpio_we_i),. Wb_stb_i (Wire_gpio_stb_i),. wb_d At_o (Wire_gpio_data_o),. Wb_ack_o (Wire_gpio_ack_o),. Wb_err_o (Wire_gpio_err_o),. Wb_inta_o (Wire_gpio_inter Rupt),//' ifdef gpio_aux_implement////Auxiliary inputs interface//. Aux_i (),//
    
       ' ENDIF//gpio_aux_implement//External GPIO Interface. Ext_pad_i ({' B0,SW} '), . Ext_pad_o (Ledr),. Ext_padoe_o ()//,//' ifdef gpio_clkpad//. Clk_pad_i ()//' endif
    
     
    
; Uart_top U_uart (. Wb_clk_i (Clk_i),//Wishbone signals. Wb_rst_i (RST),. Wb_adr_i (WI RE_UART_ADDR_I[4:0]),. Wb_dat_i (Wire_uart_data_i),. Wb_dat_o (Wire_uart_data_o),. Wb_we_i (Wire_uart_we _i),. Wb_stb_i (Wire_uart_stb_i),. Wb_cyc_i (Wire_uart_cyc_i),. Wb_ack_o (Wire_uart_ack_o),. wb_s
    
  El_i (Wire_uart_sel_i),. Int_o (Wire_uart_interrupt),//Interrupt request/UART signals SerIal input/output. Stx_pad_o (Uart_txd),. Srx_pad_i (UART_RXD),//modem signals. Rts_ Pad_o (),. Cts_pad_i (1 ' B0),. Dtr_pad_o (),. Dsr_pad_i (1 ' B0),. Ri_pad_i (1 ' B0),. Dcd_pad_i (
    
     
    
1 ' b0/////' ifdef uart_has_baudrate_output//. Baud_o ()//' endif); Endmodule