Operating system principles

CPU operator: responsible for the operation

Controller: Control CPU operation

Register: Store middle value "very small, expensive, high speed out of memory several orders of magnitude"

"An order of magnitude 1000 times times"

Cache SRAM static first-level cache: Instruction cache, data cache, generally less than 1M, the fastest

Second-level cache:

Level Three cache:

For multicore CPUs, tier One and level two caches are exclusive, and level three caches are common.

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VGA GPU Graphics (data volume is very large, speed is very block)

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cpu====> data Bus "North Bridge" data bus <==== Memory "RAM" dynamic DRAM

FSB front-end Bus | |

V-welded on the motherboard called the controller

"South Bridge" plug-in device called adapter

External device (I/O) Keyboard IDE (SATA) PCI MOUSE

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Interrupt Controller = = Interrupt number (vector) function: Let the CPU stop

Interrupt Register = = Command Counter = = Field protection

I/O prot <1~65535> functions: Enabling data exchange

The data is read into memory and then read into memory. Resume execution on return interrupt, onsite recovery.

Read into memory immediately after the execution, depends on the post-processing mechanism.

BIOS chip, there is a program, the power is written to the memory in the most 1M space, to achieve post.

DMA: Hard disk Direct access memory (interrupt), fixed an address 16M after bios1m in memory for DMA access

In the above 17M memory for a space after the kernel for use, 32-bit system accounted for about 900M.

Then the application space is used

The MMU is responsible for the conversion of the physical address to the linear address (virtual address)

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local time of the program: loading the next process in advance

Space: Pre-and post-address of the current address is loaded to improve read speed

Any unit in memory can be cached in the cache, called a direct mapping.

Displacement strategy Lru/mru commonly used LRU

N-Way Correlation technology

1 Way associative the first address of the same interval 8 addresses (1, 8, 16, 24) can only be mapped to the same cache unit

1-Way correlation technology

2-way correlation technology ..... 8-Way correlation technology (fully correlated technology) to improve the hit unit.

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This article from "Green Forest" blog, declined reprint!

Operating system principles