(Original) Brief Introduction to FPGA simulation

FPGA simulation, mainly including FPGA manufacturer software simulation and third-party edatool simulation.

 

If you use quartuⅱ software, there are two methods: function and timing.

Function:After synthesis, execute the generate function simulation netlist to implement it, with a door latency.

Timing:It must be completed after compile, including the door latency and path latency.

 

If Modelsim edatool is used, RTL simulation, post-integrated simulation, and door-level timing simulation are available.

RTL simulation:This is unexpected for the front imitation (functional simulation.

After comprehensive simulation:This is a front simulation (functional simulation), which is relatively reliable. I think this is the function simulation estimation of Q2 software. It is mainly used to check whether there is comprehensive ambiguity.

Door-level timing simulation:This is a post-simulation (timing simulation). The simulation results are reliable, but there is no routing delay.