(Original) Customized peripherals of the system: Software Design

After completing the hardware design of the custom peripherals, you need to write software to test whether the design of the peripherals is correct.

Before doing so, you must first find out the address alignment in the nioeix. For avron slave, there are two address alignment Methods: Dynamic address alignment and static address alignment.

Dynamic address alignment: the dynamic address alignment can automatically adapt to devices with different width from the aveon master port, while the increase in address length is measured in bytes. Dynamic address alignment can be used to match master and slave with different port widths to obtain a continuous storage space. However, dynamic address alignment works when reading data. When a 32-bit NiO II core reads an 8-bit slave, the physical system will generate four eight-bit read operations, while reading a 16-bit slave, two read operations are required. Peripherals of most register types cannot tolerate this attachment, so dynamic address alignment is generally not suitable for register peripherals, mainly used for storage devices. If the width of the external storage is greater than 8 bits, for example, 16 bits or 32 bits, there must be byte enable signals for the write operation at the byte granularity. Therefore, when performing interfaces for these storages, if dynamic address alignment is used, the byte enabling signal must be connected.

Static address alignment: the unit of address growth for static address alignment is the port width of the avron master. Each read/write operation only corresponds to one operation. However, the address cannot be automatically adjusted when the master and slave addresses with different port widths are matched. Some addresses do not have corresponding physical entities. When a 32-bit NiO II core reads an 8-bit slave, the 32-bit low 8-bit data is obtained from slave, while the 24-bit high data is not defined. Similarly, when it reads a 16-width slave, the 32-bit low 16-bit data is obtained from the slave, while the 16-bit high data is not defined. When you want to continue reading the next 8-bit (or 16-bit), you need to increase the byte address by 4. Unless you need a continuous address space, static address alignment is safer.

During the debugging, the following problem occurs: IOWR (keyboard_base,) is used; The IRQ interrupt signal is clear, and the SignalTap II logic analyzer cannot catch the write signal and keeps the write signal low, later, IOWR (keyboard_base, 0, 0) will be able to capture the write signal. I think it must be the problem of address alignment. Then I open the system-based file system builder and prepare the address alignment method. However, I have never seen that option. This option was available in the previous version 6.0. After a day, I had to read the official documents of Altera and finally found the answer.

So I decided to find the source file and modify it.CodeIn the generated key_h1_tcl

# Set_interface_property avalon_slave addressalignment dynamic

Set_interface_property avalon_slave addressalignment native

Comment out dynamic and change it to native.

Re-compile, the problem will not be satisfied, use SignalTap II to capture the write Signal

Test SourceProgramAs follows:

1 # Include " System. h "
2 # Include < Stdio. h >
3 # Include < Io. h >
4 # Include " Alt_types.h "
5 # Include " Sys/alt_irq.h "
6 Static   Void Key_isr ( Void * Context, alt_u32 ID );
7 Volatile   Int Irq_capture;
8 Int Main ( Void ) _ Attribute _ (weak, alias ( " Alt_main " )));
9 Int Alt_main ( Void )
10 {
11 Alt_irq_init (alt_irq_base ); // Enable interruption
12 Alt_irq_register (keyboard_irq, null, key_isr ); // Register the interrupted service program
13 While ( 1 );
14 Return   0 ;
15 }
16   Static   Void Key_isr ( Void * Context, alt_u32 ID)
17 {
18 Irq_capture = Iord (keyboard_base, 1 );
19 IOWR (keyboard_base, 2 , 0 );
20 Printf ( " Key_value: % d \ n " , Irq_capture );
21 }
22

In order to clarify the interrupted workflow, it is decided to perform one-step debugging. However, you must first know how to control and execute interruptions.

Interrupt is controlled by three registers: State, ienable, and ipending.

State:Last pie, interrupt switch, 1: interrupt enable. 0: Disable external interruption

Ipending: 32If the nth bit is 1, the nth interrupt is being processed.

Ienable: 32BITs, each1Bit1The enable bits of the external interrupt source.NBit:1, The corresponding interrupt is0The corresponding interruption is prohibited.

Note that ienable is changed to 0x4, and is associated with the last (original) Customized peripherals of the system: hardware design, with the interrupt Number 2, indicating that the keyboard interrupt is enabled.

There is also the terminal vector table alt_irq, with a total of 32, each corresponding to an interrupt priority. If the interrupt registration is successful, ISR and context will be written to the interrupt vector table.

For example, the handler of alt_irq [2] points to the key_isr () interrupt service program, and the interrupt registration is successful!

ContextThe value is 0, because the context parameter set when the program registers the interrupted service program is null.

Alt_irq_activeIs a 32-bit global variable. When an interrupt is enabled, the corresponding bit is 1.

Start running the program on the hardware, and let the program execute key_isr () to interrupt the service program. The output is as follows:

The interrupted service program is successfully executed !!

After debugging the customized peripheral software and hardware, it is really amazing that the flexibility of the system is very flexible!