Original [FPGA] Odd division of clock divider (5-way)

Use two count modules to count each, get two waveforms for basic and or complete operation. Directly post the code section below.

1 ModuleDiv_freq (2 ICLK,3 Irst_n,4 OCLK5 );6  7 input    WireICLK;8 input    WireIrst_n;9 OutputOCLK;Ten   One parameterN =4'd5; A   - Regclk_p; - Reg[3:0] cnt_p; the  always@ (PosedgeIclkor NegedgeIrst_n)begin -     if(!irst_n) -Cnt_p <=4'D0; -     Else if(cnt_p = = N-1) +Cnt_p <=4'D0; -     Else +Cnt_p <= cnt_p +1'B1; A End at  always@ (PosedgeIclkor NegedgeIrst_n)begin -     if(!irst_n) -Clk_p <=1'B0; -     Else if(cnt_p = = (N-1) /2) -Clk_p <= ~clk_p; -     Else if(cnt_p = = N-1) inClk_p <= ~clk_p; -     Else toClk_p <=clk_p; + End -   the   * RegClk_n; $ Reg[3:0] Cnt_n;Panax Notoginseng  always@ (NegedgeIclkor NegedgeIrst_n)begin -     if(!irst_n) theCnt_n <=4'D0; +     Else if(Cnt_n = = N-1) ACnt_n <=4'D0; the     Else +Cnt_n <= Cnt_n +1'B1; - End $  always@ (NegedgeIclkor NegedgeIrst_n)begin $     if(!irst_n) -Clk_n <=1'B0; -     Else if(Cnt_n = = (N-1) /2) theClk_n <= ~Clk_n; -     Else if(Cnt_n = = N-1)WuyiClk_n <= ~Clk_n; the     Else -Clk_n <=Clk_n; Wu End -   About AssignOCLK = Clk_p |Clk_n; $   - Endmodule -         

Modelsim simulation results such as

Original [FPGA] Odd division of clock divider (5-way)