(Original) How can we determine the invalid parameter information of the "leaving target processor paused" of the niosii? (IC design) (Quartus II) (FPGA builder) (Ni

Abstract
The "leaving target processor paused" is a critical component that many beginners of niosii encounter. This article provides a solution.

Environment: US us 6.0 SP1 + niosii 6.0 + de2 (Cyclone II ep2c35f627c6)

Introduction
C ++ in the template section, there is a serious cause: Compiler's response was very debugging, many developers avoided the template. The same is true for niosii, where the warning messages are unknown. Beginners often see the following warning messages.

There are many reasons for this warning, but it is a pity that the cause of this warning is not explicitly indicated in the warning message, I don't know how to debug it for beginners.

Solution
Check the following settings in sequence:

1. Set unused pins to tri-stated in Quartus II
Assignments-> Device

The setteing dialog box appears. Press Device & pin options.

The device & pin Options dialog box appears. reserve all unused pins: select as input tri-stated.

2. Set singnal to assign in Quartus II Project

(This parameter must be set only when the target board is set in the System Builder. If the target board is unspecified, no such parameter is set .)

3. Pin assignment must be added to CLK and reset_n.
Beginners often forget to add pin assignment to CLK and reset_n. The Pin assignment of CLK is pin_n2 (50 MHz) in de2. This is no problem, but what should reset_n answer? Very tricky here,Be sure to connect the key !! Switch Connection unavailable !!

Pins. TCL

CMP add_assignment " Hello_world "   ""   " CLK "   " Location "   " Pin_n2 "
CMP add_assignment " Hello_world "   ""   " Reset_n "   " Location "   " Pin_g26 "

Conclusion
This is my experience with Quartus II, the system builder, and the Nios II blogs. I was also wondering if there was a problem with the de2 development edition. After five releases, it indicates that the problem is fixed. In fact, the EDA tool Quartus II still does not have software development tools that are as mature as Visual Studio does. Visual Studio has a very clear understanding of these tools, it is easy to perform debugging Based on zookeeper, but the zookeeper messages of Quartus II and niosii are vague, it is entirely necessary to rely on the "economic" and the "economic" without making any mistakes.

See also
(originally known) How can we determine the semi-complete information of the timestamp of the niosii that does not match? (IC design) (de2) (nio ii) (SOPC us II) (FPGA builder)
(formerly known) de2_nios_lite 1.0 (SOC) (de2)
(original topology) How can we determine the distributed aggregate interest (ii) of the "leaving target processor paused" of the niosii )? (SOC) (nio ii) (DE2-70)
(formerly known) How to Determine "timestamp value does not match: image on board is older than expected "cannot receive messages? (SOC) (nio ii)