(Original) How can we determine the valid parameter information (ii) of the "leaving target processor paused" of the niosii )? (SOC) (nano II) (System Builder) (DE2-70)

Abstract
"Leaving target processor paused" is a warning message that many beginners of nioii often encounter. I met again today. I will share my debugging process with you.

Introduction
Use environment: Quartus II 8.0 + DE2-70 (Cyclone II ep2c70f896c6n)+ TRDB-LTM

In the (original scheme), how does one determine the valid parameter information of the "leaving target processor paused" of the niosii? In the (IC design) (SOPC us II) (Systems builder) (nioii), I have discussed the methods commonly used to solve the "leaving target processor paused" problem, however, there are many reasons for this negative response, which can only be solved in case by case. Today, it is easy to use this negative response, then, I will share with you the debugging method.

Response Message

In this line

Verify failed Between Address Zero X 4000000   And   0x400f547

We have already told us that there is an issue in the 0x4000000 and 0x400f547 region, and we can quickly launch the system based on the following:

It turns out that there is a problem with SDRAM !!At least the target has been set to SDRAM !!

If you directly use the reference design of the niosii to develop the niosii, such as (original release) de2_nios_lite 1.1 (SOC) (μ c/OS-II) (de2) or (original) where there is a DE2-70 of the niosii reference design can be admitted? (SOC) (DE2-70) (nio ii), you will not encounter this problem, because these examples have been done for your SDRAM, but if you're adding the original de2/DE2-70 example yourself with the niosii, then maybe you're just like me, the SDRAM originally controlled by sdram_control_4port must be changed to the SDRAM controlled by aveon bus. At this time, the pin memory of the SDRAM must be reconnected by itself.

1 De2_70_ts-nios0 (
2 // 1) Global signals:
3 . Clk_50 (iclk_50 ),
4 . Pll_c0_system (cpu_clk ),
5 . Pll_c1_memory (sram_clk ),
6 . Pll_c2_audio (oaud_xck ), // Clk_18m324 ),
7 . Reset_n (cpu_reset_n ),
8 // The_sdram (U1)
9 . Zs_addr_from_the_sdram_u1 (odram0_a ),
10 . Zs_ba_from_the_sdram_u1 (odram0_ba ),
11 . Zs_cas_n_from_the_sdram_u1 (odram0_cas_n ),
12 . Zs_cke_from_the_sdram_u1 (odram0_cke ),
13 . Zs_cs_n_from_the_sdram_u1 (odram0_cs_n ),
14 . Zs_dq_to_and_from_the_sdram_u1 (dram_dq [ 15 : 0 ]),
15 . Zs_dqm_from_the_sdram_u1 ({odram0_udqm1, odram0_ldqm0 }),
16 . Zs_ras_n_from_the_sdram_u1 (odram0_ras_n ),
17 . Zs_we_n_from_the_sdram_u1 (odram0_we_n ),
18 // The_sdram (U2)
19 . Zs_addr_from_the_sdram_u2 (odram1_a ),
20 . Zs_ba_from_the_sdram_u2 (odramstmba ),
21 . Zs_cas_n_from_the_sdram_u2 (odram1_cas_n ),
22 . Zs_cke_from_the_sdram_u2 (odram1_cke ),
23 . Zs_cs_n_from_the_sdram_u2 (odram1_cs_n ),
24 . Zs_dq_to_and_from_the_sdram_u2 (dram_dq [ 31 : 16 ]),
25 . Zs_dqm_from_the_sdram_u2 ({odram1_udqm1, odram1_ldqm0 }),
26 . Zs_ras_n_from_the_sdram_u2 (odram?ras_n ),
27 . Zs_we_n_from_the_sdram_u2 (odram1_we_n ),
28 // The_tristate_bridge_avalon_slave (flash)
29 . Address_to_the_cfi_flash ({oflash_a [ 21 : 0 ], Flash_16bit_ip_a0 }),
30 . Data_to_and_from_the_cfi_flash ({flash_dq15_am1, flash_dq }),
31 . Read_n_to_the_cfi_flash (oflash_oe_n ),
32 . Select_n_to_the_cfi_flash (oflash_ce_n ),
33 . Write_n_to_the_cfi_flash (oflash_we_n ),
34 // The_tristate_bridge_incluavalon_slave (ssram)
35 . Address_to_the_ssram ({osram_a [ 17 : 0 ], Sram_dummy_addr }),
36 . Adsc_n_to_the_ssram (osram_adsc_n ),
37 . Bw_n_to_the_ssram (osram_be_n ),
38 . Bwe_n_to_the_ssram (osram_we_n ),
39 . Chipenablepolicn_to_the_ssram (osram_ce0000n ),
40 . Data_to_and_from_the_ssram (sram_dq )),
41 . Outputenable_n_to_the_ssram (osram_oe_n ),
42 );
43

At first glance, everything is normal, and all the SDRAM pin segments are taken over by the system. If you think so, as I did, I will encounter the warning message of "leaving target processor paused.

Solution
The reason is that two other ports forgot to be specified:

// SDRAM
Assign Odram0_clk = Sram_clk; // Sdram0 clock
Assign Odram1_clk = Sram_clk; // Sdram1 clock

After these two clock blocks are mounted, the result will be normal.

Download the complete program
De2_70_d5m_ltm_nios_ltm_master.7z

Conclusion
The "leaving target processor paused" is a warning message that beginners often encounter. After passing through the failed address, you can at least set the debug goal to an IP address, it may be a question of C, but it may be a question of OpenGL. Like I forgot to specify the clock of the SDRAM, it is easy to ignore the clock. If you encounter the Clock of the SDRAM, do not forget to check whether it is the same as me, forgot to specify the SDRAM clock.

See also
(originally known) How does one determine the principal loss of the "leaving target processor paused" of the niosii? (IC design) (Quartus II) (FPGA builder) (nios_lite II)
(original release) de2_nios_lite 1.1 (SOC) (μ c/OS-II) (de2)
(original) which has the DE2-70 of the nioii reference design can be admitted? (SOC) (DE2-70: image on board is older than expected "cannot receive messages? (SOC) (nio ii)