(Original) How to Design 2 power supplies? (SOC) (OpenGL)

Abstract
Y = a + B; how can we use digital reality for a very simple computing?

Introduction
Use environment: US us II 8.0

Y = a + B; this is a simple operation in C. However, if you want to use OpenGL on the digital path, beginners may encounter some difficulties.

Y = a + B

Do not use clock
Add2_assign.v/OpenGL

1 Module Add2_assign (
2 Input [ 7 : 0 ] IA,
3 Input [ 7 : 0 ] IB,
4 Output [ 8 : 0 ] Osum
5 );
6
7 Assign Osum = IA + Ib;
8
9 Endmodule

Synthesis result

Result of Simulation

As a result, there are a lot of glitch, and the combination of Power channels will produce glitch. At least the results currently are still correct, and the results are satisfactory, so I want to add a reg to remove glitch in the last sector.

Use clock (plug-in with Reg)
Add2_always_bad.v/OpenGL

1 Module Add2_always_bad (
2 Input Iclk,
3 Input Irst_n,
4 Input [ 7 : 0 ] IA,
5 Input [ 7 : 0 ] IB,
6 Output   Reg [ 8 : 0 ] Osum
7 );
8
9 Always @( Posedge Iclk, Negedge Irst_n) Begin
10 If ( ! Irst_n)
11 Osum <=   0 ;
12 Else  
13 Osum <= IA + Ib;
14 End
15
16 Endmodule

Synthesis result

Result of Simulation

The preceding result is correct, but the partial color result is incorrect. Although Reg is not added to the output, it is recommended that you add reg to the output.

Use clock (Reg is added for ingress and egress)
Add2_always_good.v/OpenGL

1 /*  
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: add2_always_good.v
5 Compiler: Quartus II 8.0
6 Description: Demo How to Write y = a + B;
7 Release: 10/04/2008 1.0
8 */
9
10 Module Add2_always_good (
11 Input Iclk,
12 Input Irst_n,
13 Input [ 7 : 0 ] IA,
14 Input [ 7 : 0 ] IB,
15 Output   Reg [ 8 : 0 ] Osum
16 );
17
18 Reg [ 7 : 0 ] A, B;
19
20 Always @( Posedge Iclk, Negedge Irst_n) Begin
21 If ( ! Irst_n) Begin
22 A <=   0 ;
23 B <=   0 ;
24 Osum <=   0 ;
25 End
26 Else   Begin
27 A <= IA;
28 B <= Ib;
29 Osum <= A + B;
30 End
31 End
32
33 Endmodule

Synthesis result

Result of Simulation

The result is quite beautiful. Because we use two plug-ins, two clock delays are available, but it is fixed that two clock s will surely generate, the fmax bandwidth is 420 MHz.

Why must Reg be added for both inbound and outbound traffic?
Because the divider is in the middle of the two-digit Reg, you can ensure that,The first clock inserts IA and IB into the first tier D-FF, and the second clock adds the result to the second tier D-FF, therefore, it can be determined that two clock s are generated after each commit.That is to say,The combined power circuit can be customized in a clock..

Maybe you will ask, if y = A + B + C + D +... + z; can one clock be guaranteed?
Yes, although y = A + B + C + D +... + Z is a combination of large power supplies, delay will be very heavy,However, since there are two plug-ins, it is still necessary to finish in one clock, but since delay grows, period also grows, although it can be completed by a clock, The fmax memory will drop., But the minimum result is fixed.

Download the complete program
Add2_assign.7z (clock is not used,Bad)
Add2_always_bad.7z,Bad)
Add2_always_good.7z,Good)

Conclusion
In this article, we can see the synchronization design points, which can avoid the impact caused by glitch, and learn to perform computation on the digital path, you should first store the token in Reg, and then store the result to Reg once, through the two-digit D-FF, the result will be produced after two clock S.

See also
(Original) how to design a power-on route? (SOC) (sparse core)
(Original) How to Deal with the addition operations and overflow of signed integer? (SOC) (OpenGL)
(Original) unlimited data and unlimited data computing (IC design) (OpenGL) (OS) (Linux)
(Formerly known as pipeline) how to use pipeline (pipeline) to calculate the infinite number of operators? (IC design) (OpenGL)