[Original]. How to Run μC/OS-II

Hardware: Amy ep2c8 FPGA-NiO Development Board with 8 Mb SDRAM and epcs4 on board

Software: qii + NII sbte 9.1 SP1

Hardware part 1: build the system-based system-wide network interface 1. Create a qii project and other projects (1) create a qii Project

Figure 1-1 create a qii Project

(2) Select a device

Figure 1-2 select a device

(3) other settings

Figure 1-3 set no pins to three-state input

Figure 1-4 set the as configuration chip to epcs4

2. Build the niosii Soft Core (1) Open the FPGA builder to create a soft-core system.

Figure 2-1 create a soft-core system

Because I want to run the SDRAM to 125 MHz, first modify the soft core input clock frequency to 125 MHz.

Figure 2-2 modify the soft core input clock frequency

(2) Add processors and memory

Configure the SDRAM controller. Here the use of SDRAM is Samsung's K4S641632K-UC60: 64 Mbit; 16 Bit Width; maximum operating frequency is 166 MHz, CL = 3.

Figure 2-3 configure the SDRAM mode to 16 Bit

Figure 2-3 configure SDRAM Cl = 3

Figure 2-4 configure the Reset vector and exception vector of the processor

(3) Add the interval timer Core

This core must be added because sys_clk_timer is required for the μ c/OS-II.

Figure 2-5 configure the interval timer Core

(4) add other cores required for debugging

Figure 2-6 add other cores required for debugging

Note: Have you noticed that all components are automatically followed by a number, "_ 0", which is ugly. In fact, because each component is converted into an HDL file, multiple Enis or other Enis can be built in a system, it will overwrite each other so that the compilation is wrong. Of course, it is okay to remove a single core.

(5) automatically allocate the base address and interrupt number

Figure 2-7 automatically allocate the base address and interrupt number

(6) Compile the soft-core system

Omitted

3. Compile the qii Project (1) configure the Phase-Locked Loop

The input is a 50 MHz clock, and two MHz clock are output. One of them is a phase lag of-3.5ns, which is used as the clock of SDRAM. The top-level module must be described using the language of OpenGL. Therefore, when generating the PLL ing file, you need to make the following options.

Figure 3-1 select the output sample template file and the pixel box file

(2) edit the top-level module

Create a new OpenGL file and name it the same as the project name. Set* _ Inst. v(Sdram_pll_inst.v, nios_core_0_inst.v)CodeCopy it in.

Code 1 ucos_ii_test.v prototype

Sdram_pll sdram_pll_inst (. inclk0 (inclk0_sig ),. c0 (c0_sig ),. c1 (c1_sig); // example instantiation for system 'nios_core_0 'nios_core_0_inst (. clk_0 (clk_0 ),. reset_n (reset_n ),. zs_addr_from_the_sdram_0 (zs_addr_from_the_sdram_0 ),. zs_ba_from_the_sdram_0 (zs_ba_from_the_sdram_0 ),. zs_cas_n_from_the_sdram_0 (zs_cas_n_from_the_sdram_0 ),. zs_cke_from_the_sdram_0 (zs_cke_from_the_sdram_0 ),. zs_cs_n_from_the_sdram_0 (zs_cs_n_from_the_sdram_0 ),. zs_dq_to_and_from_the_sdram_0 (zs_dq_to_and_from_the_sdram_0 ),. zs_dqm_from_the_sdram_0 (zs_dqm_from_the_sdram_0 ),. zs_ras_n_from_the_sdram_0 (zs_ras_n_from_the_sdram_0 ),. zs_we_n_from_the_sdram_0 (zs_we_n_from_the_sdram_0 ));
 

With the sample templates of these modules, we only need to add the input and output declarations and make slight changes.

Code 2 ucos_ii_test.v

Module ucos_ii_test (// clock _ INPUT clock_50, // SDRAM output [11: 0] sdram_addr, output [1:0] sdram_ba, output records, output sdram_clk, output sdram_cke, output records, inout [] sdram_dq, output [1:0] sdram_dqm, output sdram_ras_n, output sdram_we_n); wire nios_core_clk; sdram_pll sdram_pll_inst (. inclk0 (clock_50 ),. c0 (nios_core_clk ),. c1 (sdram_clk); nios_core_0 nios_core_0_inst (//. clk_0 (nios_core_clk ),//. reset_n (1' B1 ),. zs_addr_from_the_sdram_0 (sdram_addr ),. zs_ba_from_the_sdram_0 (sdram_ba ),. zs_cas_n_from_the_sdram_0 (sdram_cas_n ),. zs_cke_from_the_sdram_0 (sdram_cke ),. zs_cs_n_from_the_sdram_0 (sdram_cs_n ),. zs_dq_to_and_from_the_sdram_0 (sdram_dq ),. zs_dqm_from_the_sdram_0 (sdram_dqm ),. zs_ras_n_from_the_sdram_0 (sdram_ras_n ),. zs_we_n_from_the_sdram_0 (sdram_we_n); endmodule

Compile the generated RTL view.

Figure 3-2 RTL view of the project

(3) PIN allocation

Refer to [original]. two common methods for Pin allocation in Quartus II. [Quartus II]

 

2. Software 1. Use a template to create a software project

Figure 1-1 create a software project using a template

Figure 1-2 select Hello microc/OS-II Template

2. compile software engineering

Figure 2-1 compile a software project

3. Run the project

Figure 3-1 select the hardware to run the niosii

Figure 3-2 check whether the JTAG connection is correct

Run it.

4. view the running result

Figure 4-1 execution result of the template

So far, a can run the μC/OS-II platform is built. To study the μC/OS-II in depth, you only need to increase or decrease the corresponding C code.

5. Appendix: Template code

# Include <stdio. h> # include "includes. H "/* Definition of task stacks */# define task_stacksize 2048os_stk task1_stk [task_stacksize]; OS _stk task2_stk [task_stacksize]; /* Definition of task priorities */# define task1_priority 1 # define task2_priority 2/* prints "Hello World" and sleeps for three seconds */void task1 (void * pdata) {While (1) {printf ("hello from task1 \ n"); ostimedlyhmsm (0, 0, 3, 0 );}} /* prints "Hello World" and sleeps for three seconds */void task2 (void * pdata) {While (1) {printf ("hello from task2 \ n "); ostimedlyhmsm (0, 0, 3, 0) ;}/ * The main function creates two task and starts multi-tasking */INT main (void) {ostaskcreateext (task1, null, (void *) & task1_stk [TASK_STACKSIZE-1], task1_priority, task1_priority, task1_stk, task_stacksize, null, 0); ostaskcreateext (task2, null, (void *) & task2_stk [TASK_STACKSIZE-1], task2_priority, task2_priority, task2_stk, task_stacksize, null, 0); osstart (); Return 0 ;}

Three descriptions

Note: sys_clk_timer is the component necessary to run the μ c/OS-II. Why does a delay reset module apply to the PLL? I guess the PLL initialization of Cyclone II is very fast. A stable clock source can be output without too much latency, but I am not sure whether it is so. I will study it later.

In addition, using HDL to describe top-level files is much easier than the schematic description. We recommend that you use HDL.

Iv. References

1 Altera. Hello microc/OS-II

2 Altera. Using the microc/OS-II RTOS with the nano II processor tutorial

3 Altera. microc/OS-II real time operating system

4 [original]. two common methods for Pin allocation in Quartus II. [Quartus II]