(Original) PCI bus features and signal description

 

This article introduces

Recently, CPCI was used in the project, and the information about PCI was collected online. CPCI is a subset of PCI. The bridge chip used is divided into two types: master and slave. As for PCI, I will describe it as follows:

 

With the rapid development of Windows Graphical User interfaces and the wide application of multimedia technology, the system requires high-speed graphic processing and I/O throughput, this makes the original ISA and eisa bus far from being able to adapt and become the main bottleneck of the entire system. To this end, in the second half of 1991, Intel first proposed the concept of PCI, and joined more than 100 companies, including IBM, Compaq, AST, HP apple, NCR, and Dec, to seek the development of computer bus, the PCI group was established.

PCI:Peripheral Component Interconnect, peripheral device Interconnection BusIt is a local bus and has become a new standard for local bus. It is widely used in high-end microcomputer, workstation, and portable microcomputer. It is mainly used to connect the display card, Nic, and sound card. PCI bus is a 32-bit synchronous multiplexing bus. Its address and data line pin are ad31 ~ Ad0. The operating frequency of PCI is 33 MHz.

PCI bus features

1. PCI bus features
(1) high transmission rate The maximum data transmission rate is 132 Mb/s. When the data width is upgraded to 64-bit, the data transmission rate can reach 264 Mb/s. This is incomparable to other bus. It greatly relieves the bottleneck of data I/O, makes full use of high-performance CPU functions, and adapts to the needs of high-speed equipment data transmission.
(2) coexistence of multiple Bus A pci bus can coexist multiple bus types in a system, allowing devices at different speeds to work together. Through the HOST-PCI bridge component chip, the CPU bus and PCI Bus Bridge; through the PCI-ISA/EISA bridge component chip, the PCI bus and ISA/EISA Bus Bridge, constitute a hierarchical multi-bus system. High-speed devices are removed from the ISA/eisa bus and moved to the PCI bus. The low-speed devices can still be mounted on the ISA/eisa bus, inheriting the original resources and expanding system compatibility.
(3) independent from CPU The PCI bus is not attached to a specific processor. That is, the PCI bus supports multiple processors and new processors that will be developed in the future. when changing the processor type, replace the corresponding bridging component.
(4) Automatic Identification and configuration of peripherals Easy to use.
(5) Parallel Operation Capability.
2. Main Performance of PCI bus
(1) bus clock frequency: 33.3 MHz/66.6 MHz.
(2) The bus width is 32-bit/64-bit.
(3) the maximum data transmission rate is 132 Mb/s (264 Mb/s ).
(4) supports 64-bit addressing.
(5) applicable to 5 V and 3 V power supply environments.

2. PCI bus Signal

The signal lines defined by the PCI bus standard are generally divided into required and optional categories. The total number of signal lines is 120 (including power supply, ground, reserved pin, etc ). Among them, the signal line is required: 49 for the master device and 47 for the target device. Optional signal lines: 51 (mainly used for 64-bit extension, interrupt request, and high-speed cache support ).
A master device is a device with control over the bus. A device selected by the master device for data exchange is called a slave device or a target device. As the main device, 49 signal lines are required. If the device is the target device, 47 signal lines are required. The optional signal lines include 51. Using these signal lines, you can transmit data and addresses to implement interface control, arbitration, and system functions. Shows the PCI local bus signal. The following sections describe the function groups.

1. System Signal
CLK in: System clock signal To provide time series for all PCI transmission, and input signals for all PCI devices. The maximum frequency is 33 MHz/66 MHz, which is also known as the operating frequency of PCI.
RST # in: Reset signal. Used to force all registers, sequencers, and signals dedicated to PCI to the initial state.
2. Address and data signal
AD [31: 00] t/s: Address and data multiplexing Signals . The address and data transmission on the PCI bus must be performed during frame #'s validity period. When frame # is effective at 1st clocks, the signal on AD [31: 00] is the address signal, which is called the address period. When irdy # And trdy # are both valid, the signal on AD [31: 00] is a data signal, called a data period. A pci bus transmission cycle contains one address period and one or more subsequent data periods.
C/be [3: 0] # t/s: Bus commands and bytes allow multiplexing of Signals . During the address period, these four bus commands are transmitted online; during the data period, they are transmitted in bytes to allow signals, used to specify the data period, AD [31 :: 00] which of the four online data bytes are valid for transmission.
Par t/s: Parity Signal . It performs parity through ad [31: 00] and C/be [3: 0. The master device is the address cycle and write data cycle drive par, And the slave device is the read data cycle drive par.
3. interface control signal
Frame # S/t/s: Frame cycle signal, driven by the main device . Indicates the start time and duration of a bus transmission. When frame # is valid, it indicates the start of bus transmission. During its validity period, it first transmits the address and then data. When frame # is withdrawn, it indicates that bus transmission is complete, when irdy # is valid, data transmission is performed for the last data period.
Irdy # S/t/s: Signal preparation for the master device . Irdy # Must be used together with trdy #. when both are valid, the data can be transmitted. Otherwise, the waiting period is not ready for the second. In the write cycle, when the signal is valid, it indicates that the data has been submitted to the Active AD [31: 00] line by the master device. During the reading cycle, when the signal is valid, indicates that the master device is ready to receive data.
Trdy # S/t/s: Prepare signals from the device (selected device) . Similarly, trdy # Must be used together with irdy #. data can be transmitted only when both are valid.
Stop # S/t/s: The signal from the device that requires the master device to stop the current data transmission . Apparently, the signal should be sent from the device.
Lock # S/t/s: Lock Signal . When performing an operation on a device that may require multiple bus transmission cycles, use the lock signal lock # for dedicated access. For example, if a device has its own memory, it must be able to be locked to achieve completely dedicated access to the memory. That is to say, the operations on this device are exclusive.
Idsel in: Initialize the device selection signal. It is used as a chip selection signal during parameter configuration read/write transmission.
Devsel # S/t/s: Device selection Signal . This signal is sent when the slave device identifies the address. When the signal is valid, it indicates that a certain device on the bus has been selected and serves as the currently accessed slave device.
4. Arbitration signal (for bus master controller only)
REQ # t/s: Request signal occupied by bus . This signal effectively indicates that the device that drives it requires the use of the bus. It is a point-to-point signal line, and any master device has its own req # signal.
GnT # t/s: Permitted signal occupied by bus . This signal is valid, indicating that the request for a device occupying the bus has been obtained.
5. Error Reporting Signal
Perr # S/t/s: Data parity error report Signal . A device can report a Perr # only when it responds to the selected signal (devsel #) and completes the data period #.
Serr # O/D: System Error Reporting Signal . Report address parity errors, data parity errors in special command sequences, and other system errors that may cause catastrophic consequences. It can be sent by any device.
6. Interrupt Signal In the PCI bus, interruption is optional and not necessarily required.
INTA # O/D: Used for request interruption.
Intb # O/D, intc # O/D, intd # O/D: Used for request interruption, which is only valid for the multi-function device. A multi-functional device is a device that integrates several independent functions. The connection between each function and the disconnection is arbitrary and there are no additional restrictions.
7. other optional Signals
(1) Support signals for high-speed cache: SBO # in/out and sdone in/out
(2) extended 64-bit bus signal: req64 # S/t/s, ack65 # S/t/s, AD [63 :: 32] T/S, C/be [7: 4] # t/s, par64 t/s.
(3) Test Access Port/Boundary Scan signals: TCK in, TDI in, TDO out, TMS in, and trst # In.